sc_err_t err;
sc_ipc_t ipc;
- sc_pin_t pin_id = pad & PIN_ID_MASK;
+ sc_pad_t pin_id = pad & PIN_ID_MASK;
uint32_t val = (uint32_t)((pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT);
while (count < msg->size)
{
MU_HAL_ReceiveMsg(base, count % MU_RR_COUNT,
- &(msg->DATA.d32[count - 1]));
+ &(msg->DATA.u32[count - 1]));
count++;
}
while (count < msg->size)
{
MU_HAL_SendMsg(base, count % MU_TR_COUNT,
- msg->DATA.d32[count - 1]);
+ msg->DATA.u32[count - 1]);
count++;
}
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_IRQ;
RPC_FUNC(&msg) = IRQ_FUNC_ENABLE;
- RPC_D32(&msg, 0) = mask;
- RPC_D16(&msg, 4) = resource;
- RPC_D8(&msg, 6) = group;
- RPC_D8(&msg, 7) = enable;
+ RPC_U32(&msg, 0) = mask;
+ RPC_U16(&msg, 4) = resource;
+ RPC_U8(&msg, 6) = group;
+ RPC_U8(&msg, 7) = enable;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_IRQ;
RPC_FUNC(&msg) = IRQ_FUNC_STATUS;
- RPC_D16(&msg, 0) = resource;
- RPC_D8(&msg, 2) = group;
+ RPC_U16(&msg, 0) = resource;
+ RPC_U8(&msg, 2) = group;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
if (status != NULL)
- *status = RPC_D32(&msg, 0);
+ *status = RPC_U32(&msg, 0);
result = RPC_R8(&msg);
return (sc_err_t) result;
}
MISC_FUNC_SET_ARI = 3, /*!< Index for misc_set_ari() RPC call */
MISC_FUNC_BOOT_STATUS = 7, /*!< Index for misc_boot_status() RPC call */
MISC_FUNC_OTP_FUSE_READ = 11, /*!< Index for misc_otp_fuse_read() RPC call */
+ MISC_FUNC_SET_TEMP = 12, /*!< Index for misc_set_temp() RPC call */
+ MISC_FUNC_GET_TEMP = 13, /*!< Index for misc_get_temp() RPC call */
} misc_func_t;
/* Functions */
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = MISC_FUNC_SET_CONTROL;
- RPC_D32(&msg, 0) = ctrl;
- RPC_D32(&msg, 4) = val;
- RPC_D16(&msg, 8) = resource;
+ RPC_U32(&msg, 0) = ctrl;
+ RPC_U32(&msg, 4) = val;
+ RPC_U16(&msg, 8) = resource;
RPC_SIZE(&msg) = 4;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = MISC_FUNC_GET_CONTROL;
- RPC_D32(&msg, 0) = ctrl;
- RPC_D16(&msg, 4) = resource;
+ RPC_U32(&msg, 0) = ctrl;
+ RPC_U16(&msg, 4) = resource;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
if (val != NULL)
- *val = RPC_D32(&msg, 0);
+ *val = RPC_U32(&msg, 0);
result = RPC_R8(&msg);
return (sc_err_t) result;
}
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = MISC_FUNC_SET_MAX_DMA_GROUP;
- RPC_D8(&msg, 0) = pt;
- RPC_D8(&msg, 1) = max;
+ RPC_U8(&msg, 0) = pt;
+ RPC_U8(&msg, 1) = max;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = MISC_FUNC_SET_DMA_GROUP;
- RPC_D16(&msg, 0) = resource;
- RPC_D8(&msg, 2) = group;
+ RPC_U16(&msg, 0) = resource;
+ RPC_U8(&msg, 2) = group;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = MISC_FUNC_SECO_IMAGE_LOAD;
- RPC_D32(&msg, 0) = addr_src;
- RPC_D32(&msg, 4) = addr_dst;
- RPC_D32(&msg, 8) = len;
- RPC_D8(&msg, 12) = fw;
+ RPC_U32(&msg, 0) = addr_src;
+ RPC_U32(&msg, 4) = addr_dst;
+ RPC_U32(&msg, 8) = len;
+ RPC_U8(&msg, 12) = fw;
RPC_SIZE(&msg) = 5;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = MISC_FUNC_SECO_AUTHENTICATE;
- RPC_D32(&msg, 0) = addr_meta;
- RPC_D8(&msg, 4) = cmd;
+ RPC_U32(&msg, 0) = addr_meta;
+ RPC_U8(&msg, 4) = cmd;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = MISC_FUNC_DEBUG_OUT;
- RPC_D8(&msg, 0) = ch;
+ RPC_U8(&msg, 0) = ch;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = MISC_FUNC_WAVEFORM_CAPTURE;
- RPC_D8(&msg, 0) = enable;
+ RPC_U8(&msg, 0) = enable;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = MISC_FUNC_SET_ARI;
- RPC_D16(&msg, 0) = resource;
- RPC_D16(&msg, 2) = resource_mst;
- RPC_D16(&msg, 4) = ari;
- RPC_D8(&msg, 6) = enable;
+ RPC_U16(&msg, 0) = resource;
+ RPC_U16(&msg, 2) = resource_mst;
+ RPC_U16(&msg, 4) = ari;
+ RPC_U8(&msg, 6) = enable;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = MISC_FUNC_BOOT_STATUS;
- RPC_D8(&msg, 0) = status;
+ RPC_U8(&msg, 0) = status;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, true);
sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val)
{
sc_rpc_msg_t msg;
- uint32_t result;
+ uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = MISC_FUNC_OTP_FUSE_READ;
- RPC_D32(&msg, 0) = word;
+ RPC_U32(&msg, 0) = word;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
- result = RPC_D32(&msg, 0);
if (val != NULL)
- *val = RPC_D32(&msg, 4);
+ *val = RPC_U32(&msg, 0);
+ result = RPC_R8(&msg);
+ return (sc_err_t) result;
+}
+
+sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_misc_temp_t temp, int16_t celsius, int8_t tenths)
+{
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = MISC_FUNC_SET_TEMP;
+ RPC_U16(&msg, 0) = resource;
+ RPC_I16(&msg, 2) = celsius;
+ RPC_U8(&msg, 4) = temp;
+ RPC_I8(&msg, 5) = tenths;
+ RPC_SIZE(&msg) = 3;
+
+ sc_call_rpc(ipc, &msg, false);
+
+ result = RPC_R8(&msg);
+ return (sc_err_t) result;
+}
+
+sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_misc_temp_t temp, int16_t *celsius, int8_t *tenths)
+{
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = MISC_FUNC_GET_TEMP;
+ RPC_U16(&msg, 0) = resource;
+ RPC_U8(&msg, 2) = temp;
+ RPC_SIZE(&msg) = 2;
+
+ sc_call_rpc(ipc, &msg, false);
+
+ if (celsius != NULL)
+ *celsius = RPC_I16(&msg, 0);
+ result = RPC_R8(&msg);
+ if (tenths != NULL)
+ *tenths = RPC_I8(&msg, 2);
return (sc_err_t) result;
}
/* Local Functions */
-sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pin_t pin,
+sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad,
uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso)
{
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = PAD_FUNC_SET_MUX;
- RPC_D16(&msg, 0) = pin;
- RPC_D8(&msg, 2) = mux;
- RPC_D8(&msg, 3) = config;
- RPC_D8(&msg, 4) = iso;
+ RPC_U16(&msg, 0) = pad;
+ RPC_U8(&msg, 2) = mux;
+ RPC_U8(&msg, 3) = config;
+ RPC_U8(&msg, 4) = iso;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
return (sc_err_t) result;
}
-sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pin_t pin,
+sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad,
uint8_t *mux, sc_pad_config_t *config, sc_pad_iso_t *iso)
{
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = PAD_FUNC_GET_MUX;
- RPC_D16(&msg, 0) = pin;
+ RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
if (mux != NULL)
- *mux = RPC_D8(&msg, 0);
+ *mux = RPC_U8(&msg, 0);
if (config != NULL)
- *config = RPC_D8(&msg, 1);
+ *config = RPC_U8(&msg, 1);
if (iso != NULL)
- *iso = RPC_D8(&msg, 2);
+ *iso = RPC_U8(&msg, 2);
return (sc_err_t) result;
}
-sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pin_t pin, uint32_t ctrl)
+sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = PAD_FUNC_SET_GP;
- RPC_D32(&msg, 0) = ctrl;
- RPC_D16(&msg, 4) = pin;
+ RPC_U32(&msg, 0) = ctrl;
+ RPC_U16(&msg, 4) = pad;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
return (sc_err_t) result;
}
-sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pin_t pin, uint32_t *ctrl)
+sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = PAD_FUNC_GET_GP;
- RPC_D16(&msg, 0) = pin;
+ RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
if (ctrl != NULL)
- *ctrl = RPC_D32(&msg, 0);
+ *ctrl = RPC_U32(&msg, 0);
result = RPC_R8(&msg);
return (sc_err_t) result;
}
-sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pin_t pin,
+sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_wakeup_t wakeup)
{
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = PAD_FUNC_SET_WAKEUP;
- RPC_D16(&msg, 0) = pin;
- RPC_D8(&msg, 2) = wakeup;
+ RPC_U16(&msg, 0) = pad;
+ RPC_U8(&msg, 2) = wakeup;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
return (sc_err_t) result;
}
-sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pin_t pin,
+sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_wakeup_t *wakeup)
{
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = PAD_FUNC_GET_WAKEUP;
- RPC_D16(&msg, 0) = pin;
+ RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
if (wakeup != NULL)
- *wakeup = RPC_D8(&msg, 0);
+ *wakeup = RPC_U8(&msg, 0);
return (sc_err_t) result;
}
-sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pin_t pin, uint8_t mux,
+sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux,
sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
sc_pad_wakeup_t wakeup)
{
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = PAD_FUNC_SET_ALL;
- RPC_D32(&msg, 0) = ctrl;
- RPC_D16(&msg, 4) = pin;
- RPC_D8(&msg, 6) = mux;
- RPC_D8(&msg, 7) = config;
- RPC_D8(&msg, 8) = iso;
- RPC_D8(&msg, 9) = wakeup;
+ RPC_U32(&msg, 0) = ctrl;
+ RPC_U16(&msg, 4) = pad;
+ RPC_U8(&msg, 6) = mux;
+ RPC_U8(&msg, 7) = config;
+ RPC_U8(&msg, 8) = iso;
+ RPC_U8(&msg, 9) = wakeup;
RPC_SIZE(&msg) = 4;
sc_call_rpc(ipc, &msg, false);
return (sc_err_t) result;
}
-sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pin_t pin, uint8_t *mux,
+sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux,
sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl,
sc_pad_wakeup_t *wakeup)
{
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = PAD_FUNC_GET_ALL;
- RPC_D16(&msg, 0) = pin;
+ RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
if (ctrl != NULL)
- *ctrl = RPC_D32(&msg, 0);
+ *ctrl = RPC_U32(&msg, 0);
result = RPC_R8(&msg);
if (mux != NULL)
- *mux = RPC_D8(&msg, 4);
+ *mux = RPC_U8(&msg, 4);
if (config != NULL)
- *config = RPC_D8(&msg, 5);
+ *config = RPC_U8(&msg, 5);
if (iso != NULL)
- *iso = RPC_D8(&msg, 6);
+ *iso = RPC_U8(&msg, 6);
if (wakeup != NULL)
- *wakeup = RPC_D8(&msg, 7);
+ *wakeup = RPC_U8(&msg, 7);
return (sc_err_t) result;
}
-sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pin_t pin, uint32_t val)
+sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, uint32_t val)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = PAD_FUNC_SET;
- RPC_D32(&msg, 0) = val;
- RPC_D16(&msg, 4) = pin;
+ RPC_U32(&msg, 0) = val;
+ RPC_U16(&msg, 4) = pad;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
return (sc_err_t) result;
}
-sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pin_t pin, uint32_t *val)
+sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = PAD_FUNC_GET;
- RPC_D16(&msg, 0) = pin;
+ RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
if (val != NULL)
- *val = RPC_D32(&msg, 0);
+ *val = RPC_U32(&msg, 0);
result = RPC_R8(&msg);
return (sc_err_t) result;
}
-sc_err_t sc_pad_set_gp_28lpp(sc_ipc_t ipc, sc_pin_t pin,
+sc_err_t sc_pad_set_gp_28lpp(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28lpp_dse_t dse, bool sre, bool hys, bool pe,
sc_pad_28lpp_ps_t ps)
{
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = PAD_FUNC_SET_GP_28LPP;
- RPC_D16(&msg, 0) = pin;
- RPC_D8(&msg, 2) = dse;
- RPC_D8(&msg, 3) = ps;
- RPC_D8(&msg, 4) = sre;
- RPC_D8(&msg, 5) = hys;
- RPC_D8(&msg, 6) = pe;
+ RPC_U16(&msg, 0) = pad;
+ RPC_U8(&msg, 2) = dse;
+ RPC_U8(&msg, 3) = ps;
+ RPC_U8(&msg, 4) = sre;
+ RPC_U8(&msg, 5) = hys;
+ RPC_U8(&msg, 6) = pe;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
return (sc_err_t) result;
}
-sc_err_t sc_pad_get_gp_28lpp(sc_ipc_t ipc, sc_pin_t pin,
+sc_err_t sc_pad_get_gp_28lpp(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28lpp_dse_t *dse, bool *sre, bool *hys, bool *pe,
sc_pad_28lpp_ps_t *ps)
{
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = PAD_FUNC_GET_GP_28LPP;
- RPC_D16(&msg, 0) = pin;
+ RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
if (dse != NULL)
- *dse = RPC_D8(&msg, 0);
+ *dse = RPC_U8(&msg, 0);
if (ps != NULL)
- *ps = RPC_D8(&msg, 1);
+ *ps = RPC_U8(&msg, 1);
if (sre != NULL)
- *sre = RPC_D8(&msg, 2);
+ *sre = RPC_U8(&msg, 2);
if (hys != NULL)
- *hys = RPC_D8(&msg, 3);
+ *hys = RPC_U8(&msg, 3);
if (pe != NULL)
- *pe = RPC_D8(&msg, 4);
+ *pe = RPC_U8(&msg, 4);
return (sc_err_t) result;
}
-sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pin_t pin,
+sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps)
{
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = PAD_FUNC_SET_GP_28FDSOI;
- RPC_D16(&msg, 0) = pin;
- RPC_D8(&msg, 2) = dse;
- RPC_D8(&msg, 3) = ps;
+ RPC_U16(&msg, 0) = pad;
+ RPC_U8(&msg, 2) = dse;
+ RPC_U8(&msg, 3) = ps;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
return (sc_err_t) result;
}
-sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pin_t pin,
+sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps)
{
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = PAD_FUNC_GET_GP_28FDSOI;
- RPC_D16(&msg, 0) = pin;
+ RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
if (dse != NULL)
- *dse = RPC_D8(&msg, 0);
+ *dse = RPC_U8(&msg, 0);
if (ps != NULL)
- *ps = RPC_D8(&msg, 1);
+ *ps = RPC_U8(&msg, 1);
return (sc_err_t) result;
}
-sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pin_t pin,
+sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
uint8_t compen, bool fastfrz, uint8_t rasrcp, uint8_t rasrcn,
bool nasrc_sel)
{
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = PAD_FUNC_SET_GP_28FDSOI_COMP;
- RPC_D16(&msg, 0) = pin;
- RPC_D8(&msg, 2) = compen;
- RPC_D8(&msg, 3) = rasrcp;
- RPC_D8(&msg, 4) = rasrcn;
- RPC_D8(&msg, 5) = fastfrz;
- RPC_D8(&msg, 6) = nasrc_sel;
+ RPC_U16(&msg, 0) = pad;
+ RPC_U8(&msg, 2) = compen;
+ RPC_U8(&msg, 3) = rasrcp;
+ RPC_U8(&msg, 4) = rasrcn;
+ RPC_U8(&msg, 5) = fastfrz;
+ RPC_U8(&msg, 6) = nasrc_sel;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
return (sc_err_t) result;
}
-sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pin_t pin,
+sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
uint8_t *compen, bool *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn,
bool *nasrc_sel, bool *compok, uint8_t *nasrc)
{
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = PAD_FUNC_GET_GP_28FDSOI_COMP;
- RPC_D16(&msg, 0) = pin;
+ RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
if (compen != NULL)
- *compen = RPC_D8(&msg, 0);
+ *compen = RPC_U8(&msg, 0);
if (rasrcp != NULL)
- *rasrcp = RPC_D8(&msg, 1);
+ *rasrcp = RPC_U8(&msg, 1);
if (rasrcn != NULL)
- *rasrcn = RPC_D8(&msg, 2);
+ *rasrcn = RPC_U8(&msg, 2);
if (nasrc != NULL)
- *nasrc = RPC_D8(&msg, 3);
+ *nasrc = RPC_U8(&msg, 3);
if (fastfrz != NULL)
- *fastfrz = RPC_D8(&msg, 4);
+ *fastfrz = RPC_U8(&msg, 4);
if (nasrc_sel != NULL)
- *nasrc_sel = RPC_D8(&msg, 5);
+ *nasrc_sel = RPC_U8(&msg, 5);
if (compok != NULL)
- *compok = RPC_D8(&msg, 6);
+ *compok = RPC_U8(&msg, 6);
return (sc_err_t) result;
}
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PM;
RPC_FUNC(&msg) = PM_FUNC_SET_SYS_POWER_MODE;
- RPC_D8(&msg, 0) = pt;
- RPC_D8(&msg, 1) = mode;
+ RPC_U8(&msg, 0) = pt;
+ RPC_U8(&msg, 1) = mode;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PM;
RPC_FUNC(&msg) = PM_FUNC_GET_SYS_POWER_MODE;
- RPC_D8(&msg, 0) = pt;
+ RPC_U8(&msg, 0) = pt;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
if (mode != NULL)
- *mode = RPC_D8(&msg, 0);
+ *mode = RPC_U8(&msg, 0);
return (sc_err_t) result;
}
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PM;
RPC_FUNC(&msg) = PM_FUNC_SET_RESOURCE_POWER_MODE;
- RPC_D16(&msg, 0) = resource;
- RPC_D8(&msg, 2) = mode;
+ RPC_U16(&msg, 0) = resource;
+ RPC_U8(&msg, 2) = mode;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PM;
RPC_FUNC(&msg) = PM_FUNC_GET_RESOURCE_POWER_MODE;
- RPC_D16(&msg, 0) = resource;
+ RPC_U16(&msg, 0) = resource;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
if (mode != NULL)
- *mode = RPC_D8(&msg, 0);
+ *mode = RPC_U8(&msg, 0);
return (sc_err_t) result;
}
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PM;
RPC_FUNC(&msg) = PM_FUNC_SET_CLOCK_RATE;
- RPC_D32(&msg, 0) = *rate;
- RPC_D16(&msg, 4) = resource;
- RPC_D8(&msg, 6) = clk;
+ RPC_U32(&msg, 0) = *rate;
+ RPC_U16(&msg, 4) = resource;
+ RPC_U8(&msg, 6) = clk;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
- *rate = RPC_D32(&msg, 0);
+ *rate = RPC_U32(&msg, 0);
result = RPC_R8(&msg);
return (sc_err_t) result;
}
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PM;
RPC_FUNC(&msg) = PM_FUNC_GET_CLOCK_RATE;
- RPC_D16(&msg, 0) = resource;
- RPC_D8(&msg, 2) = clk;
+ RPC_U16(&msg, 0) = resource;
+ RPC_U8(&msg, 2) = clk;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
if (rate != NULL)
- *rate = RPC_D32(&msg, 0);
+ *rate = RPC_U32(&msg, 0);
result = RPC_R8(&msg);
return (sc_err_t) result;
}
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PM;
RPC_FUNC(&msg) = PM_FUNC_CLOCK_ENABLE;
- RPC_D16(&msg, 0) = resource;
- RPC_D8(&msg, 2) = clk;
- RPC_D8(&msg, 3) = enable;
- RPC_D8(&msg, 4) = autog;
+ RPC_U16(&msg, 0) = resource;
+ RPC_U8(&msg, 2) = clk;
+ RPC_U8(&msg, 3) = enable;
+ RPC_U8(&msg, 4) = autog;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PM;
RPC_FUNC(&msg) = PM_FUNC_SET_CLOCK_PARENT;
- RPC_D16(&msg, 0) = resource;
- RPC_D8(&msg, 2) = clk;
- RPC_D8(&msg, 3) = parent;
+ RPC_U16(&msg, 0) = resource;
+ RPC_U8(&msg, 2) = clk;
+ RPC_U8(&msg, 3) = parent;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PM;
RPC_FUNC(&msg) = PM_FUNC_GET_CLOCK_PARENT;
- RPC_D16(&msg, 0) = resource;
- RPC_D8(&msg, 2) = clk;
+ RPC_U16(&msg, 0) = resource;
+ RPC_U8(&msg, 2) = clk;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
if (parent != NULL)
- *parent = RPC_D8(&msg, 0);
+ *parent = RPC_U8(&msg, 0);
return (sc_err_t) result;
}
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PM;
RPC_FUNC(&msg) = PM_FUNC_RESET;
- RPC_D8(&msg, 0) = type;
+ RPC_U8(&msg, 0) = type;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
if (reason != NULL)
- *reason = RPC_D8(&msg, 0);
+ *reason = RPC_U8(&msg, 0);
return (sc_err_t) result;
}
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PM;
RPC_FUNC(&msg) = PM_FUNC_BOOT;
- RPC_D32(&msg, 0) = boot_addr >> 32;
- RPC_D32(&msg, 4) = boot_addr;
- RPC_D16(&msg, 8) = resource_cpu;
- RPC_D16(&msg, 10) = resource_mu;
- RPC_D16(&msg, 12) = resource_dev;
- RPC_D8(&msg, 14) = pt;
+ RPC_U32(&msg, 0) = boot_addr >> 32;
+ RPC_U32(&msg, 4) = boot_addr;
+ RPC_U16(&msg, 8) = resource_cpu;
+ RPC_U16(&msg, 10) = resource_mu;
+ RPC_U16(&msg, 12) = resource_dev;
+ RPC_U8(&msg, 14) = pt;
RPC_SIZE(&msg) = 5;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PM;
RPC_FUNC(&msg) = PM_FUNC_REBOOT;
- RPC_D8(&msg, 0) = type;
+ RPC_U8(&msg, 0) = type;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, true);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PM;
RPC_FUNC(&msg) = PM_FUNC_REBOOT_PARTITION;
- RPC_D8(&msg, 0) = pt;
- RPC_D8(&msg, 1) = type;
+ RPC_U8(&msg, 0) = pt;
+ RPC_U8(&msg, 1) = type;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PM;
RPC_FUNC(&msg) = PM_FUNC_CPU_START;
- RPC_D32(&msg, 0) = address >> 32;
- RPC_D32(&msg, 4) = address;
- RPC_D16(&msg, 8) = resource;
- RPC_D8(&msg, 10) = enable;
+ RPC_U32(&msg, 0) = address >> 32;
+ RPC_U32(&msg, 4) = address;
+ RPC_U16(&msg, 8) = resource;
+ RPC_U8(&msg, 10) = enable;
RPC_SIZE(&msg) = 4;
sc_call_rpc(ipc, &msg, false);
RM_FUNC_SET_MEMREG_PERMISSIONS = 20, /*!< Index for rm_set_memreg_permissions() RPC call */
RM_FUNC_IS_MEMREG_OWNED = 21, /*!< Index for rm_is_memreg_owned() RPC call */
RM_FUNC_GET_MEMREG_INFO = 22, /*!< Index for rm_get_memreg_info() RPC call */
- RM_FUNC_ASSIGN_PIN = 23, /*!< Index for rm_assign_pin() RPC call */
- RM_FUNC_SET_PIN_MOVABLE = 24, /*!< Index for rm_set_pin_movable() RPC call */
- RM_FUNC_IS_PIN_OWNED = 25, /*!< Index for rm_is_pin_owned() RPC call */
+ RM_FUNC_ASSIGN_PAD = 23, /*!< Index for rm_assign_pad() RPC call */
+ RM_FUNC_SET_PAD_MOVABLE = 24, /*!< Index for rm_set_pad_movable() RPC call */
+ RM_FUNC_IS_PAD_OWNED = 25, /*!< Index for rm_is_pad_owned() RPC call */
} rm_func_t;
/* Functions */
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_PARTITION_ALLOC;
- RPC_D8(&msg, 0) = secure;
- RPC_D8(&msg, 1) = isolated;
- RPC_D8(&msg, 2) = restricted;
- RPC_D8(&msg, 3) = confidential;
- RPC_D8(&msg, 4) = coherent;
+ RPC_U8(&msg, 0) = secure;
+ RPC_U8(&msg, 1) = isolated;
+ RPC_U8(&msg, 2) = restricted;
+ RPC_U8(&msg, 3) = confidential;
+ RPC_U8(&msg, 4) = coherent;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
if (pt != NULL)
- *pt = RPC_D8(&msg, 0);
+ *pt = RPC_U8(&msg, 0);
return (sc_err_t) result;
}
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_PARTITION_FREE;
- RPC_D8(&msg, 0) = pt;
+ RPC_U8(&msg, 0) = pt;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_PARTITION_STATIC;
- RPC_D8(&msg, 0) = pt;
- RPC_D8(&msg, 1) = did;
+ RPC_U8(&msg, 0) = pt;
+ RPC_U8(&msg, 1) = did;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_PARTITION_LOCK;
- RPC_D8(&msg, 0) = pt;
+ RPC_U8(&msg, 0) = pt;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
if (pt != NULL)
- *pt = RPC_D8(&msg, 0);
+ *pt = RPC_U8(&msg, 0);
return (sc_err_t) result;
}
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_SET_PARENT;
- RPC_D8(&msg, 0) = pt;
- RPC_D8(&msg, 1) = pt_parent;
+ RPC_U8(&msg, 0) = pt;
+ RPC_U8(&msg, 1) = pt_parent;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
}
sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst,
- bool move_rsrc, bool move_pins)
+ bool move_rsrc, bool move_pads)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_MOVE_ALL;
- RPC_D8(&msg, 0) = pt_src;
- RPC_D8(&msg, 1) = pt_dst;
- RPC_D8(&msg, 2) = move_rsrc;
- RPC_D8(&msg, 3) = move_pins;
+ RPC_U8(&msg, 0) = pt_src;
+ RPC_U8(&msg, 1) = pt_dst;
+ RPC_U8(&msg, 2) = move_rsrc;
+ RPC_U8(&msg, 3) = move_pads;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_ASSIGN_RESOURCE;
- RPC_D16(&msg, 0) = resource;
- RPC_D8(&msg, 2) = pt;
+ RPC_U16(&msg, 0) = resource;
+ RPC_U8(&msg, 2) = pt;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_SET_RESOURCE_MOVABLE;
- RPC_D16(&msg, 0) = resource_fst;
- RPC_D16(&msg, 2) = resource_lst;
- RPC_D8(&msg, 4) = movable;
+ RPC_U16(&msg, 0) = resource_fst;
+ RPC_U16(&msg, 2) = resource_lst;
+ RPC_U8(&msg, 4) = movable;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_SET_MASTER_ATTRIBUTES;
- RPC_D16(&msg, 0) = resource;
- RPC_D8(&msg, 2) = sa;
- RPC_D8(&msg, 3) = pa;
- RPC_D8(&msg, 4) = smmu_bypass;
+ RPC_U16(&msg, 0) = resource;
+ RPC_U8(&msg, 2) = sa;
+ RPC_U8(&msg, 3) = pa;
+ RPC_U8(&msg, 4) = smmu_bypass;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_SET_MASTER_SID;
- RPC_D16(&msg, 0) = resource;
- RPC_D16(&msg, 2) = sid;
+ RPC_U16(&msg, 0) = resource;
+ RPC_U16(&msg, 2) = sid;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_SET_PERIPHERAL_PERMISSIONS;
- RPC_D16(&msg, 0) = resource;
- RPC_D8(&msg, 2) = pt;
- RPC_D8(&msg, 3) = perm;
+ RPC_U16(&msg, 0) = resource;
+ RPC_U8(&msg, 2) = pt;
+ RPC_U8(&msg, 3) = perm;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_IS_RESOURCE_OWNED;
- RPC_D16(&msg, 0) = resource;
+ RPC_U16(&msg, 0) = resource;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_IS_RESOURCE_MASTER;
- RPC_D16(&msg, 0) = resource;
+ RPC_U16(&msg, 0) = resource;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_IS_RESOURCE_PERIPHERAL;
- RPC_D16(&msg, 0) = resource;
+ RPC_U16(&msg, 0) = resource;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_GET_RESOURCE_INFO;
- RPC_D16(&msg, 0) = resource;
+ RPC_U16(&msg, 0) = resource;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
if (sid != NULL)
- *sid = RPC_D16(&msg, 0);
+ *sid = RPC_U16(&msg, 0);
result = RPC_R8(&msg);
return (sc_err_t) result;
}
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_MEMREG_ALLOC;
- RPC_D32(&msg, 0) = addr_start >> 32;
- RPC_D32(&msg, 4) = addr_start;
- RPC_D32(&msg, 8) = addr_end >> 32;
- RPC_D32(&msg, 12) = addr_end;
+ RPC_U32(&msg, 0) = addr_start >> 32;
+ RPC_U32(&msg, 4) = addr_start;
+ RPC_U32(&msg, 8) = addr_end >> 32;
+ RPC_U32(&msg, 12) = addr_end;
RPC_SIZE(&msg) = 5;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
if (mr != NULL)
- *mr = RPC_D8(&msg, 0);
+ *mr = RPC_U8(&msg, 0);
return (sc_err_t) result;
}
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_MEMREG_FREE;
- RPC_D8(&msg, 0) = mr;
+ RPC_U8(&msg, 0) = mr;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_ASSIGN_MEMREG;
- RPC_D8(&msg, 0) = pt;
- RPC_D8(&msg, 1) = mr;
+ RPC_U8(&msg, 0) = pt;
+ RPC_U8(&msg, 1) = mr;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_SET_MEMREG_PERMISSIONS;
- RPC_D8(&msg, 0) = mr;
- RPC_D8(&msg, 1) = pt;
- RPC_D8(&msg, 2) = perm;
+ RPC_U8(&msg, 0) = mr;
+ RPC_U8(&msg, 1) = pt;
+ RPC_U8(&msg, 2) = perm;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_IS_MEMREG_OWNED;
- RPC_D8(&msg, 0) = mr;
+ RPC_U8(&msg, 0) = mr;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
RPC_FUNC(&msg) = RM_FUNC_GET_MEMREG_INFO;
- RPC_D8(&msg, 0) = mr;
+ RPC_U8(&msg, 0) = mr;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
if (addr_start != NULL)
- *addr_start = ((uint64_t) RPC_D32(&msg, 0) << 32) | RPC_D32(&msg, 4);
+ *addr_start = ((uint64_t) RPC_U32(&msg, 0) << 32) | RPC_U32(&msg, 4);
if (addr_end != NULL)
- *addr_end = ((uint64_t) RPC_D32(&msg, 8) << 32) | RPC_D32(&msg, 12);
+ *addr_end = ((uint64_t) RPC_U32(&msg, 8) << 32) | RPC_U32(&msg, 12);
result = RPC_R8(&msg);
return (sc_err_t) result;
}
-sc_err_t sc_rm_assign_pin(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pin_t pin)
+sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_ASSIGN_PIN;
- RPC_D16(&msg, 0) = pin;
- RPC_D8(&msg, 2) = pt;
+ RPC_FUNC(&msg) = RM_FUNC_ASSIGN_PAD;
+ RPC_U16(&msg, 0) = pad;
+ RPC_U8(&msg, 2) = pt;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
return (sc_err_t) result;
}
-sc_err_t sc_rm_set_pin_movable(sc_ipc_t ipc, sc_pin_t pin_fst,
- sc_pin_t pin_lst, bool movable)
+sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst,
+ sc_pad_t pad_lst, bool movable)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_SET_PIN_MOVABLE;
- RPC_D16(&msg, 0) = pin_fst;
- RPC_D16(&msg, 2) = pin_lst;
- RPC_D8(&msg, 4) = movable;
+ RPC_FUNC(&msg) = RM_FUNC_SET_PAD_MOVABLE;
+ RPC_U16(&msg, 0) = pad_fst;
+ RPC_U16(&msg, 2) = pad_lst;
+ RPC_U8(&msg, 4) = movable;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
return (sc_err_t) result;
}
-bool sc_rm_is_pin_owned(sc_ipc_t ipc, sc_pin_t pin)
+bool sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_RM;
- RPC_FUNC(&msg) = RM_FUNC_IS_PIN_OWNED;
- RPC_D8(&msg, 0) = pin;
+ RPC_FUNC(&msg) = RM_FUNC_IS_PAD_OWNED;
+ RPC_U8(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
RPC_FUNC(&msg) = TIMER_FUNC_SET_WDOG_TIMEOUT;
- RPC_D32(&msg, 0) = timeout;
+ RPC_U32(&msg, 0) = timeout;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
RPC_FUNC(&msg) = TIMER_FUNC_START_WDOG;
- RPC_D8(&msg, 0) = lock;
+ RPC_U8(&msg, 0) = lock;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, false);
if (timeout != NULL)
- *timeout = RPC_D32(&msg, 0);
+ *timeout = RPC_U32(&msg, 0);
if (max_timeout != NULL)
- *max_timeout = RPC_D32(&msg, 4);
+ *max_timeout = RPC_U32(&msg, 4);
if (remaining_time != NULL)
- *remaining_time = RPC_D32(&msg, 8);
+ *remaining_time = RPC_U32(&msg, 8);
result = RPC_R8(&msg);
return (sc_err_t) result;
}
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
RPC_FUNC(&msg) = TIMER_FUNC_SET_RTC_TIME;
- RPC_D16(&msg, 0) = year;
- RPC_D8(&msg, 2) = mon;
- RPC_D8(&msg, 3) = day;
- RPC_D8(&msg, 4) = hour;
- RPC_D8(&msg, 5) = min;
- RPC_D8(&msg, 6) = sec;
+ RPC_U16(&msg, 0) = year;
+ RPC_U8(&msg, 2) = mon;
+ RPC_U8(&msg, 3) = day;
+ RPC_U8(&msg, 4) = hour;
+ RPC_U8(&msg, 5) = min;
+ RPC_U8(&msg, 6) = sec;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, false);
if (year != NULL)
- *year = RPC_D16(&msg, 0);
+ *year = RPC_U16(&msg, 0);
result = RPC_R8(&msg);
if (mon != NULL)
- *mon = RPC_D8(&msg, 2);
+ *mon = RPC_U8(&msg, 2);
if (day != NULL)
- *day = RPC_D8(&msg, 3);
+ *day = RPC_U8(&msg, 3);
if (hour != NULL)
- *hour = RPC_D8(&msg, 4);
+ *hour = RPC_U8(&msg, 4);
if (min != NULL)
- *min = RPC_D8(&msg, 5);
+ *min = RPC_U8(&msg, 5);
if (sec != NULL)
- *sec = RPC_D8(&msg, 6);
+ *sec = RPC_U8(&msg, 6);
return (sc_err_t) result;
}
sc_call_rpc(ipc, &msg, false);
if (sec != NULL)
- *sec = RPC_D32(&msg, 0);
+ *sec = RPC_U32(&msg, 0);
result = RPC_R8(&msg);
return (sc_err_t) result;
}
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
RPC_FUNC(&msg) = TIMER_FUNC_SET_RTC_ALARM;
- RPC_D16(&msg, 0) = year;
- RPC_D8(&msg, 2) = mon;
- RPC_D8(&msg, 3) = day;
- RPC_D8(&msg, 4) = hour;
- RPC_D8(&msg, 5) = min;
- RPC_D8(&msg, 6) = sec;
+ RPC_U16(&msg, 0) = year;
+ RPC_U8(&msg, 2) = mon;
+ RPC_U8(&msg, 3) = day;
+ RPC_U8(&msg, 4) = hour;
+ RPC_U8(&msg, 5) = min;
+ RPC_U8(&msg, 6) = sec;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
#define __ASM_ARCH_IMX8_PINS_H__
#if defined(CONFIG_IMX8QM)
-#include "imx8qm_pins.h"
+#include "imx8qm_pads.h"
#elif defined(CONFIG_IMX8QXP)
-#include "imx8qxp_pins.h"
+#include "imx8qxp_pads.h"
#else
#error "No pin header"
#endif
--- /dev/null
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*!
+ * Header file used to configure SoC pad list.
+ */
+
+#ifndef _SC_PADS_H
+#define _SC_PADS_H
+
+/* Includes */
+
+/* Defines */
+
+#define SC_P_ALL UINT16_MAX /*!< All pads */
+
+/*!
+ * @name Pad Definitions
+ */
+/*@{*/
+#define SC_P_SIM0_CLK 0 /*!< DMA.SIM0.CLK, LSIO.GPIO0.IO00 */
+#define SC_P_SIM0_RST 1 /*!< DMA.SIM0.RST, LSIO.GPIO0.IO01 */
+#define SC_P_SIM0_IO 2 /*!< DMA.SIM0.IO, LSIO.GPIO0.IO02 */
+#define SC_P_SIM0_PD 3 /*!< DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */
+#define SC_P_SIM0_POWER_EN 4 /*!< DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */
+#define SC_P_SIM0_GPIO0_00 5 /*!< DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 6 /*!< */
+#define SC_P_M40_I2C0_SCL 7 /*!< M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */
+#define SC_P_M40_I2C0_SDA 8 /*!< M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */
+#define SC_P_M40_GPIO0_00 9 /*!< M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */
+#define SC_P_M40_GPIO0_01 10 /*!< M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */
+#define SC_P_M41_I2C0_SCL 11 /*!< M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */
+#define SC_P_M41_I2C0_SDA 12 /*!< M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */
+#define SC_P_M41_GPIO0_00 13 /*!< M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */
+#define SC_P_M41_GPIO0_01 14 /*!< M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */
+#define SC_P_GPT0_CLK 15 /*!< LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */
+#define SC_P_GPT0_CAPTURE 16 /*!< LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */
+#define SC_P_GPT0_COMPARE 17 /*!< LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */
+#define SC_P_GPT1_CLK 18 /*!< LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */
+#define SC_P_GPT1_CAPTURE 19 /*!< LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */
+#define SC_P_GPT1_COMPARE 20 /*!< LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */
+#define SC_P_UART0_RX 21 /*!< DMA.UART0.RX, LSIO.GPIO0.IO20 */
+#define SC_P_UART0_TX 22 /*!< DMA.UART0.TX, LSIO.GPIO0.IO21 */
+#define SC_P_UART0_RTS_B 23 /*!< DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */
+#define SC_P_UART0_CTS_B 24 /*!< DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */
+#define SC_P_UART1_TX 25 /*!< DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */
+#define SC_P_UART1_RX 26 /*!< DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */
+#define SC_P_UART1_RTS_B 27 /*!< DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */
+#define SC_P_UART1_CTS_B 28 /*!< DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29 /*!< */
+#define SC_P_SCU_PMIC_MEMC_ON 30 /*!< SCU.GPIO0.IOXX_PMIC_MEMC_ON */
+#define SC_P_SCU_WDOG_OUT 31 /*!< SCU.WDOG0.WDOG_OUT */
+#define SC_P_PMIC_I2C_SDA 32 /*!< SCU.PMIC_I2C.SDA */
+#define SC_P_PMIC_I2C_SCL 33 /*!< SCU.PMIC_I2C.SCL */
+#define SC_P_PMIC_EARLY_WARNING 34 /*!< SCU.PMIC_EARLY_WARNING */
+#define SC_P_PMIC_INT_B 35 /*!< SCU.DSC.PMIC_INT_B */
+#define SC_P_SCU_GPIO0_00 36 /*!< SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */
+#define SC_P_SCU_GPIO0_01 37 /*!< SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */
+#define SC_P_SCU_GPIO0_02 38 /*!< SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */
+#define SC_P_SCU_GPIO0_03 39 /*!< SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */
+#define SC_P_SCU_GPIO0_04 40 /*!< SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */
+#define SC_P_SCU_GPIO0_05 41 /*!< SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */
+#define SC_P_SCU_GPIO0_06 42 /*!< SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */
+#define SC_P_SCU_GPIO0_07 43 /*!< SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */
+#define SC_P_SCU_BOOT_MODE0 44 /*!< SCU.DSC.BOOT_MODE0 */
+#define SC_P_SCU_BOOT_MODE1 45 /*!< SCU.DSC.BOOT_MODE1 */
+#define SC_P_SCU_BOOT_MODE2 46 /*!< SCU.DSC.BOOT_MODE2 */
+#define SC_P_SCU_BOOT_MODE3 47 /*!< SCU.DSC.BOOT_MODE3 */
+#define SC_P_SCU_BOOT_MODE4 48 /*!< SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */
+#define SC_P_SCU_BOOT_MODE5 49 /*!< SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */
+#define SC_P_LVDS0_GPIO00 50 /*!< LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */
+#define SC_P_LVDS0_GPIO01 51 /*!< LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */
+#define SC_P_LVDS0_I2C0_SCL 52 /*!< LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */
+#define SC_P_LVDS0_I2C0_SDA 53 /*!< LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */
+#define SC_P_LVDS0_I2C1_SCL 54 /*!< LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */
+#define SC_P_LVDS0_I2C1_SDA 55 /*!< LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */
+#define SC_P_LVDS1_GPIO00 56 /*!< LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */
+#define SC_P_LVDS1_GPIO01 57 /*!< LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */
+#define SC_P_LVDS1_I2C0_SCL 58 /*!< LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */
+#define SC_P_LVDS1_I2C0_SDA 59 /*!< LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */
+#define SC_P_LVDS1_I2C1_SCL 60 /*!< LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */
+#define SC_P_LVDS1_I2C1_SDA 61 /*!< LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62 /*!< */
+#define SC_P_MIPI_DSI0_I2C0_SCL 63 /*!< MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */
+#define SC_P_MIPI_DSI0_I2C0_SDA 64 /*!< MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */
+#define SC_P_MIPI_DSI0_GPIO0_00 65 /*!< MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */
+#define SC_P_MIPI_DSI0_GPIO0_01 66 /*!< MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */
+#define SC_P_MIPI_DSI1_I2C0_SCL 67 /*!< MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */
+#define SC_P_MIPI_DSI1_I2C0_SDA 68 /*!< MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */
+#define SC_P_MIPI_DSI1_GPIO0_00 69 /*!< MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */
+#define SC_P_MIPI_DSI1_GPIO0_01 70 /*!< MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71 /*!< */
+#define SC_P_MIPI_CSI0_MCLK_OUT 72 /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */
+#define SC_P_MIPI_CSI0_I2C0_SCL 73 /*!< MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */
+#define SC_P_MIPI_CSI0_I2C0_SDA 74 /*!< MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */
+#define SC_P_MIPI_CSI0_GPIO0_00 75 /*!< MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, LSIO.GPIO1.IO27 */
+#define SC_P_MIPI_CSI0_GPIO0_01 76 /*!< MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, LSIO.GPIO1.IO28 */
+#define SC_P_MIPI_CSI1_MCLK_OUT 77 /*!< MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */
+#define SC_P_MIPI_CSI1_GPIO0_00 78 /*!< MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */
+#define SC_P_MIPI_CSI1_GPIO0_01 79 /*!< MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */
+#define SC_P_MIPI_CSI1_I2C0_SCL 80 /*!< MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */
+#define SC_P_MIPI_CSI1_I2C0_SDA 81 /*!< MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */
+#define SC_P_HDMI_TX0_TS_SCL 82 /*!< HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */
+#define SC_P_HDMI_TX0_TS_SDA 83 /*!< HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */
+#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84 /*!< */
+#define SC_P_ESAI1_FSR 85 /*!< AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */
+#define SC_P_ESAI1_FST 86 /*!< AUD.ESAI1.FST, LSIO.GPIO2.IO05 */
+#define SC_P_ESAI1_SCKR 87 /*!< AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */
+#define SC_P_ESAI1_SCKT 88 /*!< AUD.ESAI1.SCKT, AUD.SAI2.RXC, LSIO.GPIO2.IO07 */
+#define SC_P_ESAI1_TX0 89 /*!< AUD.ESAI1.TX0, AUD.SAI2.RXD, LSIO.GPIO2.IO08 */
+#define SC_P_ESAI1_TX1 90 /*!< AUD.ESAI1.TX1, AUD.SAI2.RXFS, LSIO.GPIO2.IO09 */
+#define SC_P_ESAI1_TX2_RX3 91 /*!< AUD.ESAI1.TX2_RX3, LSIO.GPIO2.IO10 */
+#define SC_P_ESAI1_TX3_RX2 92 /*!< AUD.ESAI1.TX3_RX2, LSIO.GPIO2.IO11 */
+#define SC_P_ESAI1_TX4_RX1 93 /*!< AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */
+#define SC_P_ESAI1_TX5_RX0 94 /*!< AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */
+#define SC_P_SPDIF0_RX 95 /*!< AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */
+#define SC_P_SPDIF0_TX 96 /*!< AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */
+#define SC_P_SPDIF0_EXT_CLK 97 /*!< AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */
+#define SC_P_SPI3_SCK 98 /*!< DMA.SPI3.SCK, LSIO.GPIO2.IO17 */
+#define SC_P_SPI3_SDO 99 /*!< DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */
+#define SC_P_SPI3_SDI 100 /*!< DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */
+#define SC_P_SPI3_CS0 101 /*!< DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */
+#define SC_P_SPI3_CS1 102 /*!< DMA.SPI3.CS1, LSIO.GPIO2.IO21 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103 /*!< */
+#define SC_P_ESAI0_FSR 104 /*!< AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */
+#define SC_P_ESAI0_FST 105 /*!< AUD.ESAI0.FST, LSIO.GPIO2.IO23 */
+#define SC_P_ESAI0_SCKR 106 /*!< AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */
+#define SC_P_ESAI0_SCKT 107 /*!< AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */
+#define SC_P_ESAI0_TX0 108 /*!< AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */
+#define SC_P_ESAI0_TX1 109 /*!< AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */
+#define SC_P_ESAI0_TX2_RX3 110 /*!< AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */
+#define SC_P_ESAI0_TX3_RX2 111 /*!< AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */
+#define SC_P_ESAI0_TX4_RX1 112 /*!< AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */
+#define SC_P_ESAI0_TX5_RX0 113 /*!< AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */
+#define SC_P_MCLK_IN0 114 /*!< AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, LSIO.GPIO3.IO00 */
+#define SC_P_MCLK_OUT0 115 /*!< AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, LSIO.GPIO3.IO01 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 /*!< */
+#define SC_P_SPI0_SCK 117 /*!< DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */
+#define SC_P_SPI0_SDO 118 /*!< DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */
+#define SC_P_SPI0_SDI 119 /*!< DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */
+#define SC_P_SPI0_CS0 120 /*!< DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */
+#define SC_P_SPI0_CS1 121 /*!< DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */
+#define SC_P_SPI2_SCK 122 /*!< DMA.SPI2.SCK, LSIO.GPIO3.IO07 */
+#define SC_P_SPI2_SDO 123 /*!< DMA.SPI2.SDO, LSIO.GPIO3.IO08 */
+#define SC_P_SPI2_SDI 124 /*!< DMA.SPI2.SDI, LSIO.GPIO3.IO09 */
+#define SC_P_SPI2_CS0 125 /*!< DMA.SPI2.CS0, LSIO.GPIO3.IO10 */
+#define SC_P_SPI2_CS1 126 /*!< DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */
+#define SC_P_SAI1_RXC 127 /*!< AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */
+#define SC_P_SAI1_RXD 128 /*!< AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */
+#define SC_P_SAI1_RXFS 129 /*!< AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */
+#define SC_P_SAI1_TXC 130 /*!< AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */
+#define SC_P_SAI1_TXD 131 /*!< AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */
+#define SC_P_SAI1_TXFS 132 /*!< AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133 /*!< */
+#define SC_P_ADC_IN7 134 /*!< DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */
+#define SC_P_ADC_IN6 135 /*!< DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */
+#define SC_P_ADC_IN5 136 /*!< DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */
+#define SC_P_ADC_IN4 137 /*!< DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */
+#define SC_P_ADC_IN3 138 /*!< DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */
+#define SC_P_ADC_IN2 139 /*!< DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */
+#define SC_P_ADC_IN1 140 /*!< DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */
+#define SC_P_ADC_IN0 141 /*!< DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */
+#define SC_P_MLB_SIG 142 /*!< CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */
+#define SC_P_MLB_CLK 143 /*!< CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */
+#define SC_P_MLB_DATA 144 /*!< CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145 /*!< */
+#define SC_P_FLEXCAN0_RX 146 /*!< DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */
+#define SC_P_FLEXCAN0_TX 147 /*!< DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */
+#define SC_P_FLEXCAN1_RX 148 /*!< DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */
+#define SC_P_FLEXCAN1_TX 149 /*!< DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */
+#define SC_P_FLEXCAN2_RX 150 /*!< DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */
+#define SC_P_FLEXCAN2_TX 151 /*!< DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152 /*!< */
+#define SC_P_USB_SS3_TC0 153 /*!< DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */
+#define SC_P_USB_SS3_TC1 154 /*!< DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
+#define SC_P_USB_SS3_TC2 155 /*!< DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */
+#define SC_P_USB_SS3_TC3 156 /*!< DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 157 /*!< */
+#define SC_P_USDHC1_RESET_B 158 /*!< CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */
+#define SC_P_USDHC1_VSELECT 159 /*!< CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */
+#define SC_P_USDHC2_RESET_B 160 /*!< CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */
+#define SC_P_USDHC2_VSELECT 161 /*!< CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */
+#define SC_P_USDHC2_WP 162 /*!< CONN.USDHC2.WP, LSIO.GPIO4.IO11 */
+#define SC_P_USDHC2_CD_B 163 /*!< CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164 /*!< */
+#define SC_P_ENET0_MDIO 165 /*!< CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */
+#define SC_P_ENET0_MDC 166 /*!< CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */
+#define SC_P_ENET0_REFCLK_125M_25M 167 /*!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */
+#define SC_P_ENET1_REFCLK_125M_25M 168 /*!< CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */
+#define SC_P_ENET1_MDIO 169 /*!< CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */
+#define SC_P_ENET1_MDC 170 /*!< CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171 /*!< */
+#define SC_P_QSPI1A_SS0_B 172 /*!< LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */
+#define SC_P_QSPI1A_SS1_B 173 /*!< LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */
+#define SC_P_QSPI1A_SCLK 174 /*!< LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */
+#define SC_P_QSPI1A_DQS 175 /*!< LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */
+#define SC_P_QSPI1A_DATA3 176 /*!< LSIO.QSPI1A.DATA3, LSIO.GPIO4.IO23 */
+#define SC_P_QSPI1A_DATA2 177 /*!< LSIO.QSPI1A.DATA2, LSIO.GPIO4.IO24 */
+#define SC_P_QSPI1A_DATA1 178 /*!< LSIO.QSPI1A.DATA1, LSIO.GPIO4.IO25 */
+#define SC_P_QSPI1A_DATA0 179 /*!< LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 /*!< */
+#define SC_P_QSPI0A_DATA0 181 /*!< LSIO.QSPI0A.DATA0 */
+#define SC_P_QSPI0A_DATA1 182 /*!< LSIO.QSPI0A.DATA1 */
+#define SC_P_QSPI0A_DATA2 183 /*!< LSIO.QSPI0A.DATA2 */
+#define SC_P_QSPI0A_DATA3 184 /*!< LSIO.QSPI0A.DATA3 */
+#define SC_P_QSPI0A_DQS 185 /*!< LSIO.QSPI0A.DQS */
+#define SC_P_QSPI0A_SS0_B 186 /*!< LSIO.QSPI0A.SS0_B */
+#define SC_P_QSPI0A_SS1_B 187 /*!< LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */
+#define SC_P_QSPI0A_SCLK 188 /*!< LSIO.QSPI0A.SCLK */
+#define SC_P_QSPI0B_SCLK 189 /*!< LSIO.QSPI0B.SCLK */
+#define SC_P_QSPI0B_DATA0 190 /*!< LSIO.QSPI0B.DATA0 */
+#define SC_P_QSPI0B_DATA1 191 /*!< LSIO.QSPI0B.DATA1 */
+#define SC_P_QSPI0B_DATA2 192 /*!< LSIO.QSPI0B.DATA2 */
+#define SC_P_QSPI0B_DATA3 193 /*!< LSIO.QSPI0B.DATA3 */
+#define SC_P_QSPI0B_DQS 194 /*!< LSIO.QSPI0B.DQS */
+#define SC_P_QSPI0B_SS0_B 195 /*!< LSIO.QSPI0B.SS0_B */
+#define SC_P_QSPI0B_SS1_B 196 /*!< LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 197 /*!< */
+#define SC_P_PCIE_CTRL0_CLKREQ_B 198 /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */
+#define SC_P_PCIE_CTRL0_WAKE_B 199 /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */
+#define SC_P_PCIE_CTRL0_PERST_B 200 /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */
+#define SC_P_PCIE_CTRL1_CLKREQ_B 201 /*!< HSIO.PCIE1.CLKREQ_B, LSIO.GPIO4.IO30 */
+#define SC_P_PCIE_CTRL1_WAKE_B 202 /*!< HSIO.PCIE1.WAKE_B, LSIO.GPIO4.IO31 */
+#define SC_P_PCIE_CTRL1_PERST_B 203 /*!< HSIO.PCIE1.PERST_B, LSIO.GPIO5.IO00 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 /*!< */
+#define SC_P_USB_HSIC0_DATA 205 /*!< CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */
+#define SC_P_USB_HSIC0_STROBE 206 /*!< CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */
+#define SC_P_CALIBRATION_0_HSIC 207 /*!< */
+#define SC_P_CALIBRATION_1_HSIC 208 /*!< */
+#define SC_P_EMMC0_CLK 209 /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B */
+#define SC_P_EMMC0_CMD 210 /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO5.IO03 */
+#define SC_P_EMMC0_DATA0 211 /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */
+#define SC_P_EMMC0_DATA1 212 /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */
+#define SC_P_EMMC0_DATA2 213 /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */
+#define SC_P_EMMC0_DATA3 214 /*!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */
+#define SC_P_EMMC0_DATA4 215 /*!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */
+#define SC_P_EMMC0_DATA5 216 /*!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */
+#define SC_P_EMMC0_DATA6 217 /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */
+#define SC_P_EMMC0_DATA7 218 /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */
+#define SC_P_EMMC0_STROBE 219 /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */
+#define SC_P_EMMC0_RESET_B 220 /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO5.IO13 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 /*!< */
+#define SC_P_USDHC1_CLK 222 /*!< CONN.USDHC1.CLK */
+#define SC_P_USDHC1_CMD 223 /*!< CONN.USDHC1.CMD, LSIO.GPIO5.IO14 */
+#define SC_P_USDHC1_DATA0 224 /*!< CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */
+#define SC_P_USDHC1_DATA1 225 /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */
+#define SC_P_CTL_NAND_RE_P_N 226 /*!< */
+#define SC_P_USDHC1_DATA2 227 /*!< CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */
+#define SC_P_USDHC1_DATA3 228 /*!< CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */
+#define SC_P_CTL_NAND_DQS_P_N 229 /*!< */
+#define SC_P_USDHC1_DATA4 230 /*!< CONN.USDHC1.DATA4, CONN.NAND.CE0_B, LSIO.GPIO5.IO19 */
+#define SC_P_USDHC1_DATA5 231 /*!< CONN.USDHC1.DATA5, CONN.NAND.RE_B, LSIO.GPIO5.IO20 */
+#define SC_P_USDHC1_DATA6 232 /*!< CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */
+#define SC_P_USDHC1_DATA7 233 /*!< CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */
+#define SC_P_USDHC1_STROBE 234 /*!< CONN.USDHC1.STROBE, CONN.NAND.CE1_B, LSIO.GPIO5.IO23 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 /*!< */
+#define SC_P_USDHC2_CLK 236 /*!< CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */
+#define SC_P_USDHC2_CMD 237 /*!< CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */
+#define SC_P_USDHC2_DATA0 238 /*!< CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */
+#define SC_P_USDHC2_DATA1 239 /*!< CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */
+#define SC_P_USDHC2_DATA2 240 /*!< CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */
+#define SC_P_USDHC2_DATA3 241 /*!< CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 242 /*!< */
+#define SC_P_ENET0_RGMII_TXC 243 /*!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */
+#define SC_P_ENET0_RGMII_TX_CTL 244 /*!< CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */
+#define SC_P_ENET0_RGMII_TXD0 245 /*!< CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */
+#define SC_P_ENET0_RGMII_TXD1 246 /*!< CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */
+#define SC_P_ENET0_RGMII_TXD2 247 /*!< CONN.ENET0.RGMII_TXD2, LSIO.GPIO6.IO02 */
+#define SC_P_ENET0_RGMII_TXD3 248 /*!< CONN.ENET0.RGMII_TXD3, LSIO.GPIO6.IO03 */
+#define SC_P_ENET0_RGMII_RXC 249 /*!< CONN.ENET0.RGMII_RXC, LSIO.GPIO6.IO04 */
+#define SC_P_ENET0_RGMII_RX_CTL 250 /*!< CONN.ENET0.RGMII_RX_CTL, LSIO.GPIO6.IO05 */
+#define SC_P_ENET0_RGMII_RXD0 251 /*!< CONN.ENET0.RGMII_RXD0, LSIO.GPIO6.IO06 */
+#define SC_P_ENET0_RGMII_RXD1 252 /*!< CONN.ENET0.RGMII_RXD1, LSIO.GPIO6.IO07 */
+#define SC_P_ENET0_RGMII_RXD2 253 /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, LSIO.GPIO6.IO08 */
+#define SC_P_ENET0_RGMII_RXD3 254 /*!< CONN.ENET0.RGMII_RXD3, LSIO.GPIO6.IO09 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 /*!< */
+#define SC_P_ENET1_RGMII_TXC 256 /*!< CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */
+#define SC_P_ENET1_RGMII_TX_CTL 257 /*!< CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */
+#define SC_P_ENET1_RGMII_TXD0 258 /*!< CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */
+#define SC_P_ENET1_RGMII_TXD1 259 /*!< CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */
+#define SC_P_ENET1_RGMII_TXD2 260 /*!< CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */
+#define SC_P_ENET1_RGMII_TXD3 261 /*!< CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */
+#define SC_P_ENET1_RGMII_RXC 262 /*!< CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */
+#define SC_P_ENET1_RGMII_RX_CTL 263 /*!< CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */
+#define SC_P_ENET1_RGMII_RXD0 264 /*!< CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */
+#define SC_P_ENET1_RGMII_RXD1 265 /*!< CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */
+#define SC_P_ENET1_RGMII_RXD2 266 /*!< CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */
+#define SC_P_ENET1_RGMII_RXD3 267 /*!< CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 /*!< */
+/*@}*/
+
+#endif /* _SC_PADS_H */
+
+++ /dev/null
-/*
- * Copyright 2017 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*!
- * Header file used to configure SoC pin list.
- */
-
-#ifndef _SC_PINS_H
-#define _SC_PINS_H
-
-/* Includes */
-
-/* Defines */
-
-#define SC_P_ALL UINT16_MAX /*!< All pins */
-
-/*!
- * @name Pin Definitions
- */
-/*@{*/
-#define SC_P_SIM0_CLK 0 /*!< DMA.SIM0.CLK, LSIO.GPIO0.IO00 */
-#define SC_P_SIM0_RST 1 /*!< DMA.SIM0.RST, LSIO.GPIO0.IO01 */
-#define SC_P_SIM0_IO 2 /*!< DMA.SIM0.IO, LSIO.GPIO0.IO02 */
-#define SC_P_SIM0_PD 3 /*!< DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */
-#define SC_P_SIM0_POWER_EN 4 /*!< DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */
-#define SC_P_SIM0_GPIO0_00 5 /*!< DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 6 /*!< */
-#define SC_P_M40_I2C0_SCL 7 /*!< M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */
-#define SC_P_M40_I2C0_SDA 8 /*!< M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */
-#define SC_P_M40_GPIO0_00 9 /*!< M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */
-#define SC_P_M40_GPIO0_01 10 /*!< M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */
-#define SC_P_M41_I2C0_SCL 11 /*!< M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */
-#define SC_P_M41_I2C0_SDA 12 /*!< M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */
-#define SC_P_M41_GPIO0_00 13 /*!< M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */
-#define SC_P_M41_GPIO0_01 14 /*!< M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */
-#define SC_P_GPT0_CLK 15 /*!< LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */
-#define SC_P_GPT0_CAPTURE 16 /*!< LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */
-#define SC_P_GPT0_COMPARE 17 /*!< LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */
-#define SC_P_GPT1_CLK 18 /*!< LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */
-#define SC_P_GPT1_CAPTURE 19 /*!< LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */
-#define SC_P_GPT1_COMPARE 20 /*!< LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */
-#define SC_P_UART0_RX 21 /*!< DMA.UART0.RX, LSIO.GPIO0.IO20 */
-#define SC_P_UART0_TX 22 /*!< DMA.UART0.TX, LSIO.GPIO0.IO21 */
-#define SC_P_UART0_RTS_B 23 /*!< DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */
-#define SC_P_UART0_CTS_B 24 /*!< DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */
-#define SC_P_UART1_TX 25 /*!< DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */
-#define SC_P_UART1_RX 26 /*!< DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */
-#define SC_P_UART1_RTS_B 27 /*!< DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */
-#define SC_P_UART1_CTS_B 28 /*!< DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29 /*!< */
-#define SC_P_SCU_PMIC_MEMC_ON 30 /*!< SCU.GPIO0.IOXX_PMIC_MEMC_ON */
-#define SC_P_SCU_WDOG_OUT 31 /*!< SCU.WDOG0.WDOG_OUT */
-#define SC_P_PMIC_I2C_SDA 32 /*!< SCU.PMIC_I2C.SDA */
-#define SC_P_PMIC_I2C_SCL 33 /*!< SCU.PMIC_I2C.SCL */
-#define SC_P_PMIC_EARLY_WARNING 34 /*!< SCU.PMIC_EARLY_WARNING */
-#define SC_P_PMIC_INT_B 35 /*!< SCU.DSC.PMIC_INT_B */
-#define SC_P_SCU_GPIO0_00 36 /*!< SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */
-#define SC_P_SCU_GPIO0_01 37 /*!< SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */
-#define SC_P_SCU_GPIO0_02 38 /*!< SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */
-#define SC_P_SCU_GPIO0_03 39 /*!< SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */
-#define SC_P_SCU_GPIO0_04 40 /*!< SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */
-#define SC_P_SCU_GPIO0_05 41 /*!< SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */
-#define SC_P_SCU_GPIO0_06 42 /*!< SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */
-#define SC_P_SCU_GPIO0_07 43 /*!< SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */
-#define SC_P_SCU_BOOT_MODE0 44 /*!< SCU.DSC.BOOT_MODE0 */
-#define SC_P_SCU_BOOT_MODE1 45 /*!< SCU.DSC.BOOT_MODE1 */
-#define SC_P_SCU_BOOT_MODE2 46 /*!< SCU.DSC.BOOT_MODE2 */
-#define SC_P_SCU_BOOT_MODE3 47 /*!< SCU.DSC.BOOT_MODE3 */
-#define SC_P_SCU_BOOT_MODE4 48 /*!< SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */
-#define SC_P_SCU_BOOT_MODE5 49 /*!< SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */
-#define SC_P_LVDS0_GPIO00 50 /*!< LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */
-#define SC_P_LVDS0_GPIO01 51 /*!< LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */
-#define SC_P_LVDS0_I2C0_SCL 52 /*!< LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */
-#define SC_P_LVDS0_I2C0_SDA 53 /*!< LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */
-#define SC_P_LVDS0_I2C1_SCL 54 /*!< LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */
-#define SC_P_LVDS0_I2C1_SDA 55 /*!< LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */
-#define SC_P_LVDS1_GPIO00 56 /*!< LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */
-#define SC_P_LVDS1_GPIO01 57 /*!< LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */
-#define SC_P_LVDS1_I2C0_SCL 58 /*!< LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */
-#define SC_P_LVDS1_I2C0_SDA 59 /*!< LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */
-#define SC_P_LVDS1_I2C1_SCL 60 /*!< LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */
-#define SC_P_LVDS1_I2C1_SDA 61 /*!< LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62 /*!< */
-#define SC_P_MIPI_DSI0_I2C0_SCL 63 /*!< MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */
-#define SC_P_MIPI_DSI0_I2C0_SDA 64 /*!< MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */
-#define SC_P_MIPI_DSI0_GPIO0_00 65 /*!< MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */
-#define SC_P_MIPI_DSI0_GPIO0_01 66 /*!< MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */
-#define SC_P_MIPI_DSI1_I2C0_SCL 67 /*!< MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */
-#define SC_P_MIPI_DSI1_I2C0_SDA 68 /*!< MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */
-#define SC_P_MIPI_DSI1_GPIO0_00 69 /*!< MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */
-#define SC_P_MIPI_DSI1_GPIO0_01 70 /*!< MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71 /*!< */
-#define SC_P_MIPI_CSI0_MCLK_OUT 72 /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */
-#define SC_P_MIPI_CSI0_I2C0_SCL 73 /*!< MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */
-#define SC_P_MIPI_CSI0_I2C0_SDA 74 /*!< MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */
-#define SC_P_MIPI_CSI0_GPIO0_00 75 /*!< MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, LSIO.GPIO1.IO27 */
-#define SC_P_MIPI_CSI0_GPIO0_01 76 /*!< MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, LSIO.GPIO1.IO28 */
-#define SC_P_MIPI_CSI1_MCLK_OUT 77 /*!< MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */
-#define SC_P_MIPI_CSI1_GPIO0_00 78 /*!< MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */
-#define SC_P_MIPI_CSI1_GPIO0_01 79 /*!< MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */
-#define SC_P_MIPI_CSI1_I2C0_SCL 80 /*!< MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */
-#define SC_P_MIPI_CSI1_I2C0_SDA 81 /*!< MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */
-#define SC_P_HDMI_TX0_TS_SCL 82 /*!< HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */
-#define SC_P_HDMI_TX0_TS_SDA 83 /*!< HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */
-#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84 /*!< */
-#define SC_P_ESAI1_FSR 85 /*!< AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */
-#define SC_P_ESAI1_FST 86 /*!< AUD.ESAI1.FST, LSIO.GPIO2.IO05 */
-#define SC_P_ESAI1_SCKR 87 /*!< AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */
-#define SC_P_ESAI1_SCKT 88 /*!< AUD.ESAI1.SCKT, AUD.SAI2.RXC, LSIO.GPIO2.IO07 */
-#define SC_P_ESAI1_TX0 89 /*!< AUD.ESAI1.TX0, AUD.SAI2.RXD, LSIO.GPIO2.IO08 */
-#define SC_P_ESAI1_TX1 90 /*!< AUD.ESAI1.TX1, AUD.SAI2.RXFS, LSIO.GPIO2.IO09 */
-#define SC_P_ESAI1_TX2_RX3 91 /*!< AUD.ESAI1.TX2_RX3, LSIO.GPIO2.IO10 */
-#define SC_P_ESAI1_TX3_RX2 92 /*!< AUD.ESAI1.TX3_RX2, LSIO.GPIO2.IO11 */
-#define SC_P_ESAI1_TX4_RX1 93 /*!< AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */
-#define SC_P_ESAI1_TX5_RX0 94 /*!< AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */
-#define SC_P_SPDIF0_RX 95 /*!< AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */
-#define SC_P_SPDIF0_TX 96 /*!< AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */
-#define SC_P_SPDIF0_EXT_CLK 97 /*!< AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */
-#define SC_P_SPI3_SCK 98 /*!< DMA.SPI3.SCK, LSIO.GPIO2.IO17 */
-#define SC_P_SPI3_SDO 99 /*!< DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */
-#define SC_P_SPI3_SDI 100 /*!< DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */
-#define SC_P_SPI3_CS0 101 /*!< DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */
-#define SC_P_SPI3_CS1 102 /*!< DMA.SPI3.CS1, LSIO.GPIO2.IO21 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103 /*!< */
-#define SC_P_ESAI0_FSR 104 /*!< AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */
-#define SC_P_ESAI0_FST 105 /*!< AUD.ESAI0.FST, LSIO.GPIO2.IO23 */
-#define SC_P_ESAI0_SCKR 106 /*!< AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */
-#define SC_P_ESAI0_SCKT 107 /*!< AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */
-#define SC_P_ESAI0_TX0 108 /*!< AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */
-#define SC_P_ESAI0_TX1 109 /*!< AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */
-#define SC_P_ESAI0_TX2_RX3 110 /*!< AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */
-#define SC_P_ESAI0_TX3_RX2 111 /*!< AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */
-#define SC_P_ESAI0_TX4_RX1 112 /*!< AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */
-#define SC_P_ESAI0_TX5_RX0 113 /*!< AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */
-#define SC_P_MCLK_IN0 114 /*!< AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, LSIO.GPIO3.IO00 */
-#define SC_P_MCLK_OUT0 115 /*!< AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, LSIO.GPIO3.IO01 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 /*!< */
-#define SC_P_SPI0_SCK 117 /*!< DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */
-#define SC_P_SPI0_SDO 118 /*!< DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */
-#define SC_P_SPI0_SDI 119 /*!< DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */
-#define SC_P_SPI0_CS0 120 /*!< DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */
-#define SC_P_SPI0_CS1 121 /*!< DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */
-#define SC_P_SPI2_SCK 122 /*!< DMA.SPI2.SCK, LSIO.GPIO3.IO07 */
-#define SC_P_SPI2_SDO 123 /*!< DMA.SPI2.SDO, LSIO.GPIO3.IO08 */
-#define SC_P_SPI2_SDI 124 /*!< DMA.SPI2.SDI, LSIO.GPIO3.IO09 */
-#define SC_P_SPI2_CS0 125 /*!< DMA.SPI2.CS0, LSIO.GPIO3.IO10 */
-#define SC_P_SPI2_CS1 126 /*!< DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */
-#define SC_P_SAI1_RXC 127 /*!< AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */
-#define SC_P_SAI1_RXD 128 /*!< AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */
-#define SC_P_SAI1_RXFS 129 /*!< AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */
-#define SC_P_SAI1_TXC 130 /*!< AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */
-#define SC_P_SAI1_TXD 131 /*!< AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */
-#define SC_P_SAI1_TXFS 132 /*!< AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133 /*!< */
-#define SC_P_ADC_IN7 134 /*!< DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */
-#define SC_P_ADC_IN6 135 /*!< DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */
-#define SC_P_ADC_IN5 136 /*!< DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */
-#define SC_P_ADC_IN4 137 /*!< DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */
-#define SC_P_ADC_IN3 138 /*!< DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */
-#define SC_P_ADC_IN2 139 /*!< DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */
-#define SC_P_ADC_IN1 140 /*!< DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */
-#define SC_P_ADC_IN0 141 /*!< DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */
-#define SC_P_MLB_SIG 142 /*!< CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */
-#define SC_P_MLB_CLK 143 /*!< CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */
-#define SC_P_MLB_DATA 144 /*!< CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145 /*!< */
-#define SC_P_FLEXCAN0_RX 146 /*!< DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */
-#define SC_P_FLEXCAN0_TX 147 /*!< DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */
-#define SC_P_FLEXCAN1_RX 148 /*!< DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */
-#define SC_P_FLEXCAN1_TX 149 /*!< DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */
-#define SC_P_FLEXCAN2_RX 150 /*!< DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */
-#define SC_P_FLEXCAN2_TX 151 /*!< DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152 /*!< */
-#define SC_P_USB_SS3_TC0 153 /*!< DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */
-#define SC_P_USB_SS3_TC1 154 /*!< DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
-#define SC_P_USB_SS3_TC2 155 /*!< DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */
-#define SC_P_USB_SS3_TC3 156 /*!< DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
-#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 157 /*!< */
-#define SC_P_USDHC1_RESET_B 158 /*!< CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */
-#define SC_P_USDHC1_VSELECT 159 /*!< CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */
-#define SC_P_USDHC2_RESET_B 160 /*!< CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */
-#define SC_P_USDHC2_VSELECT 161 /*!< CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */
-#define SC_P_USDHC2_WP 162 /*!< CONN.USDHC2.WP, LSIO.GPIO4.IO11 */
-#define SC_P_USDHC2_CD_B 163 /*!< CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164 /*!< */
-#define SC_P_ENET0_MDIO 165 /*!< CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */
-#define SC_P_ENET0_MDC 166 /*!< CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */
-#define SC_P_ENET0_REFCLK_125M_25M 167 /*!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */
-#define SC_P_ENET1_REFCLK_125M_25M 168 /*!< CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */
-#define SC_P_ENET1_MDIO 169 /*!< CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */
-#define SC_P_ENET1_MDC 170 /*!< CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171 /*!< */
-#define SC_P_QSPI1A_SS0_B 172 /*!< LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */
-#define SC_P_QSPI1A_SS1_B 173 /*!< LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */
-#define SC_P_QSPI1A_SCLK 174 /*!< LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */
-#define SC_P_QSPI1A_DQS 175 /*!< LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */
-#define SC_P_QSPI1A_DATA3 176 /*!< LSIO.QSPI1A.DATA3, LSIO.GPIO4.IO23 */
-#define SC_P_QSPI1A_DATA2 177 /*!< LSIO.QSPI1A.DATA2, LSIO.GPIO4.IO24 */
-#define SC_P_QSPI1A_DATA1 178 /*!< LSIO.QSPI1A.DATA1, LSIO.GPIO4.IO25 */
-#define SC_P_QSPI1A_DATA0 179 /*!< LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 /*!< */
-#define SC_P_QSPI0A_DATA0 181 /*!< LSIO.QSPI0A.DATA0 */
-#define SC_P_QSPI0A_DATA1 182 /*!< LSIO.QSPI0A.DATA1 */
-#define SC_P_QSPI0A_DATA2 183 /*!< LSIO.QSPI0A.DATA2 */
-#define SC_P_QSPI0A_DATA3 184 /*!< LSIO.QSPI0A.DATA3 */
-#define SC_P_QSPI0A_DQS 185 /*!< LSIO.QSPI0A.DQS */
-#define SC_P_QSPI0A_SS0_B 186 /*!< LSIO.QSPI0A.SS0_B */
-#define SC_P_QSPI0A_SS1_B 187 /*!< LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */
-#define SC_P_QSPI0A_SCLK 188 /*!< LSIO.QSPI0A.SCLK */
-#define SC_P_QSPI0B_SCLK 189 /*!< LSIO.QSPI0B.SCLK */
-#define SC_P_QSPI0B_DATA0 190 /*!< LSIO.QSPI0B.DATA0 */
-#define SC_P_QSPI0B_DATA1 191 /*!< LSIO.QSPI0B.DATA1 */
-#define SC_P_QSPI0B_DATA2 192 /*!< LSIO.QSPI0B.DATA2 */
-#define SC_P_QSPI0B_DATA3 193 /*!< LSIO.QSPI0B.DATA3 */
-#define SC_P_QSPI0B_DQS 194 /*!< LSIO.QSPI0B.DQS */
-#define SC_P_QSPI0B_SS0_B 195 /*!< LSIO.QSPI0B.SS0_B */
-#define SC_P_QSPI0B_SS1_B 196 /*!< LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 197 /*!< */
-#define SC_P_PCIE_CTRL0_CLKREQ_B 198 /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */
-#define SC_P_PCIE_CTRL0_WAKE_B 199 /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */
-#define SC_P_PCIE_CTRL0_PERST_B 200 /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */
-#define SC_P_PCIE_CTRL1_CLKREQ_B 201 /*!< HSIO.PCIE1.CLKREQ_B, LSIO.GPIO4.IO30 */
-#define SC_P_PCIE_CTRL1_WAKE_B 202 /*!< HSIO.PCIE1.WAKE_B, LSIO.GPIO4.IO31 */
-#define SC_P_PCIE_CTRL1_PERST_B 203 /*!< HSIO.PCIE1.PERST_B, LSIO.GPIO5.IO00 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 /*!< */
-#define SC_P_USB_HSIC0_DATA 205 /*!< CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */
-#define SC_P_USB_HSIC0_STROBE 206 /*!< CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */
-#define SC_P_CALIBRATION_0_HSIC 207 /*!< */
-#define SC_P_CALIBRATION_1_HSIC 208 /*!< */
-#define SC_P_EMMC0_CLK 209 /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B */
-#define SC_P_EMMC0_CMD 210 /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO5.IO03 */
-#define SC_P_EMMC0_DATA0 211 /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */
-#define SC_P_EMMC0_DATA1 212 /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */
-#define SC_P_EMMC0_DATA2 213 /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */
-#define SC_P_EMMC0_DATA3 214 /*!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */
-#define SC_P_EMMC0_DATA4 215 /*!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */
-#define SC_P_EMMC0_DATA5 216 /*!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */
-#define SC_P_EMMC0_DATA6 217 /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */
-#define SC_P_EMMC0_DATA7 218 /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */
-#define SC_P_EMMC0_STROBE 219 /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */
-#define SC_P_EMMC0_RESET_B 220 /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO5.IO13 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 /*!< */
-#define SC_P_USDHC1_CLK 222 /*!< CONN.USDHC1.CLK */
-#define SC_P_USDHC1_CMD 223 /*!< CONN.USDHC1.CMD, LSIO.GPIO5.IO14 */
-#define SC_P_USDHC1_DATA0 224 /*!< CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */
-#define SC_P_USDHC1_DATA1 225 /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */
-#define SC_P_CTL_NAND_RE_P_N 226 /*!< */
-#define SC_P_USDHC1_DATA2 227 /*!< CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */
-#define SC_P_USDHC1_DATA3 228 /*!< CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */
-#define SC_P_CTL_NAND_DQS_P_N 229 /*!< */
-#define SC_P_USDHC1_DATA4 230 /*!< CONN.USDHC1.DATA4, CONN.NAND.CE0_B, LSIO.GPIO5.IO19 */
-#define SC_P_USDHC1_DATA5 231 /*!< CONN.USDHC1.DATA5, CONN.NAND.RE_B, LSIO.GPIO5.IO20 */
-#define SC_P_USDHC1_DATA6 232 /*!< CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */
-#define SC_P_USDHC1_DATA7 233 /*!< CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */
-#define SC_P_USDHC1_STROBE 234 /*!< CONN.USDHC1.STROBE, CONN.NAND.CE1_B, LSIO.GPIO5.IO23 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 /*!< */
-#define SC_P_USDHC2_CLK 236 /*!< CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */
-#define SC_P_USDHC2_CMD 237 /*!< CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */
-#define SC_P_USDHC2_DATA0 238 /*!< CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */
-#define SC_P_USDHC2_DATA1 239 /*!< CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */
-#define SC_P_USDHC2_DATA2 240 /*!< CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */
-#define SC_P_USDHC2_DATA3 241 /*!< CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 242 /*!< */
-#define SC_P_ENET0_RGMII_TXC 243 /*!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */
-#define SC_P_ENET0_RGMII_TX_CTL 244 /*!< CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */
-#define SC_P_ENET0_RGMII_TXD0 245 /*!< CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */
-#define SC_P_ENET0_RGMII_TXD1 246 /*!< CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */
-#define SC_P_ENET0_RGMII_TXD2 247 /*!< CONN.ENET0.RGMII_TXD2, LSIO.GPIO6.IO02 */
-#define SC_P_ENET0_RGMII_TXD3 248 /*!< CONN.ENET0.RGMII_TXD3, LSIO.GPIO6.IO03 */
-#define SC_P_ENET0_RGMII_RXC 249 /*!< CONN.ENET0.RGMII_RXC, LSIO.GPIO6.IO04 */
-#define SC_P_ENET0_RGMII_RX_CTL 250 /*!< CONN.ENET0.RGMII_RX_CTL, LSIO.GPIO6.IO05 */
-#define SC_P_ENET0_RGMII_RXD0 251 /*!< CONN.ENET0.RGMII_RXD0, LSIO.GPIO6.IO06 */
-#define SC_P_ENET0_RGMII_RXD1 252 /*!< CONN.ENET0.RGMII_RXD1, LSIO.GPIO6.IO07 */
-#define SC_P_ENET0_RGMII_RXD2 253 /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, LSIO.GPIO6.IO08 */
-#define SC_P_ENET0_RGMII_RXD3 254 /*!< CONN.ENET0.RGMII_RXD3, LSIO.GPIO6.IO09 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 /*!< */
-#define SC_P_ENET1_RGMII_TXC 256 /*!< CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */
-#define SC_P_ENET1_RGMII_TX_CTL 257 /*!< CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */
-#define SC_P_ENET1_RGMII_TXD0 258 /*!< CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */
-#define SC_P_ENET1_RGMII_TXD1 259 /*!< CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */
-#define SC_P_ENET1_RGMII_TXD2 260 /*!< CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */
-#define SC_P_ENET1_RGMII_TXD3 261 /*!< CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */
-#define SC_P_ENET1_RGMII_RXC 262 /*!< CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */
-#define SC_P_ENET1_RGMII_RX_CTL 263 /*!< CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */
-#define SC_P_ENET1_RGMII_RXD0 264 /*!< CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */
-#define SC_P_ENET1_RGMII_RXD1 265 /*!< CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */
-#define SC_P_ENET1_RGMII_RXD2 266 /*!< CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */
-#define SC_P_ENET1_RGMII_RXD3 267 /*!< CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 /*!< */
-/*@}*/
-
-#endif /* _SC_PINS_H */
-
--- /dev/null
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*!
+ * Header file used to configure SoC pad list.
+ */
+
+#ifndef _SC_PADS_H
+#define _SC_PADS_H
+
+/* Includes */
+
+/* Defines */
+
+#define SC_P_ALL UINT16_MAX /*!< All pads */
+
+/*!
+ * @name Pad Definitions
+ */
+/*@{*/
+#define SC_P_PCIE_CTRL0_PERST_B 0 /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */
+#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */
+#define SC_P_PCIE_CTRL0_WAKE_B 2 /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /*!< */
+#define SC_P_USB_SS3_TC0 4 /*!< ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */
+#define SC_P_USB_SS3_TC1 5 /*!< ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
+#define SC_P_USB_SS3_TC2 6 /*!< ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */
+#define SC_P_USB_SS3_TC3 7 /*!< ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 /*!< */
+#define SC_P_EMMC0_CLK 9 /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */
+#define SC_P_EMMC0_CMD 10 /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */
+#define SC_P_EMMC0_DATA0 11 /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */
+#define SC_P_EMMC0_DATA1 12 /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */
+#define SC_P_EMMC0_DATA2 13 /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */
+#define SC_P_EMMC0_DATA3 14 /*!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 /*!< */
+#define SC_P_EMMC0_DATA4 16 /*!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */
+#define SC_P_EMMC0_DATA5 17 /*!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */
+#define SC_P_EMMC0_DATA6 18 /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */
+#define SC_P_EMMC0_DATA7 19 /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */
+#define SC_P_EMMC0_STROBE 20 /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */
+#define SC_P_EMMC0_RESET_B 21 /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 /*!< */
+#define SC_P_USDHC1_RESET_B 23 /*!< CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */
+#define SC_P_USDHC1_VSELECT 24 /*!< CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */
+#define SC_P_CTL_NAND_RE_P_N 25 /*!< */
+#define SC_P_USDHC1_WP 26 /*!< CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */
+#define SC_P_USDHC1_CD_B 27 /*!< CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */
+#define SC_P_CTL_NAND_DQS_P_N 28 /*!< */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 /*!< */
+#define SC_P_USDHC1_CLK 30 /*!< CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */
+#define SC_P_USDHC1_CMD 31 /*!< CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */
+#define SC_P_USDHC1_DATA0 32 /*!< CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */
+#define SC_P_USDHC1_DATA1 33 /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */
+#define SC_P_USDHC1_DATA2 34 /*!< CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */
+#define SC_P_USDHC1_DATA3 35 /*!< CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 /*!< */
+#define SC_P_ENET0_RGMII_TXC 37 /*!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */
+#define SC_P_ENET0_RGMII_TX_CTL 38 /*!< CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */
+#define SC_P_ENET0_RGMII_TXD0 39 /*!< CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */
+#define SC_P_ENET0_RGMII_TXD1 40 /*!< CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */
+#define SC_P_ENET0_RGMII_TXD2 41 /*!< CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */
+#define SC_P_ENET0_RGMII_TXD3 42 /*!< CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 /*!< */
+#define SC_P_ENET0_RGMII_RXC 44 /*!< CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */
+#define SC_P_ENET0_RGMII_RX_CTL 45 /*!< CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */
+#define SC_P_ENET0_RGMII_RXD0 46 /*!< CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */
+#define SC_P_ENET0_RGMII_RXD1 47 /*!< CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */
+#define SC_P_ENET0_RGMII_RXD2 48 /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */
+#define SC_P_ENET0_RGMII_RXD3 49 /*!< CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 /*!< */
+#define SC_P_ENET0_REFCLK_125M_25M 51 /*!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */
+#define SC_P_ENET0_MDIO 52 /*!< CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */
+#define SC_P_ENET0_MDC 53 /*!< CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 /*!< */
+#define SC_P_ESAI0_FSR 55 /*!< ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */
+#define SC_P_ESAI0_FST 56 /*!< ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */
+#define SC_P_ESAI0_SCKR 57 /*!< ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */
+#define SC_P_ESAI0_SCKT 58 /*!< ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */
+#define SC_P_ESAI0_TX0 59 /*!< ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */
+#define SC_P_ESAI0_TX1 60 /*!< ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */
+#define SC_P_ESAI0_TX2_RX3 61 /*!< ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */
+#define SC_P_ESAI0_TX3_RX2 62 /*!< ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */
+#define SC_P_ESAI0_TX4_RX1 63 /*!< ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */
+#define SC_P_ESAI0_TX5_RX0 64 /*!< ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */
+#define SC_P_SPDIF0_RX 65 /*!< ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */
+#define SC_P_SPDIF0_TX 66 /*!< ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */
+#define SC_P_SPDIF0_EXT_CLK 67 /*!< ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 /*!< */
+#define SC_P_SPI3_SCK 69 /*!< ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */
+#define SC_P_SPI3_SDO 70 /*!< ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */
+#define SC_P_SPI3_SDI 71 /*!< ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */
+#define SC_P_SPI3_CS0 72 /*!< ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */
+#define SC_P_SPI3_CS1 73 /*!< ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */
+#define SC_P_MCLK_IN1 74 /*!< ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */
+#define SC_P_MCLK_IN0 75 /*!< ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */
+#define SC_P_MCLK_OUT0 76 /*!< ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */
+#define SC_P_UART1_TX 77 /*!< ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */
+#define SC_P_UART1_RX 78 /*!< ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */
+#define SC_P_UART1_RTS_B 79 /*!< ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */
+#define SC_P_UART1_CTS_B 80 /*!< ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 /*!< */
+#define SC_P_SAI0_TXD 82 /*!< ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */
+#define SC_P_SAI0_TXC 83 /*!< ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */
+#define SC_P_SAI0_RXD 84 /*!< ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */
+#define SC_P_SAI0_TXFS 85 /*!< ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */
+#define SC_P_SAI1_RXD 86 /*!< ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */
+#define SC_P_SAI1_RXC 87 /*!< ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */
+#define SC_P_SAI1_RXFS 88 /*!< ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */
+#define SC_P_SPI2_CS0 89 /*!< ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */
+#define SC_P_SPI2_SDO 90 /*!< ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */
+#define SC_P_SPI2_SDI 91 /*!< ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */
+#define SC_P_SPI2_SCK 92 /*!< ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */
+#define SC_P_SPI0_SCK 93 /*!< ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */
+#define SC_P_SPI0_SDI 94 /*!< ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */
+#define SC_P_SPI0_SDO 95 /*!< ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */
+#define SC_P_SPI0_CS1 96 /*!< ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */
+#define SC_P_SPI0_CS0 97 /*!< ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 /*!< */
+#define SC_P_ADC_IN1 99 /*!< ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */
+#define SC_P_ADC_IN0 100 /*!< ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */
+#define SC_P_ADC_IN3 101 /*!< ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */
+#define SC_P_ADC_IN2 102 /*!< ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */
+#define SC_P_ADC_IN5 103 /*!< ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */
+#define SC_P_ADC_IN4 104 /*!< ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */
+#define SC_P_FLEXCAN0_RX 105 /*!< ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */
+#define SC_P_FLEXCAN0_TX 106 /*!< ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */
+#define SC_P_FLEXCAN1_RX 107 /*!< ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */
+#define SC_P_FLEXCAN1_TX 108 /*!< ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */
+#define SC_P_FLEXCAN2_RX 109 /*!< ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */
+#define SC_P_FLEXCAN2_TX 110 /*!< ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */
+#define SC_P_UART0_RX 111 /*!< ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, LSIO.GPIO1.IO21 */
+#define SC_P_UART0_TX 112 /*!< ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, LSIO.GPIO1.IO22 */
+#define SC_P_UART2_TX 113 /*!< ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */
+#define SC_P_UART2_RX 114 /*!< ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 /*!< */
+#define SC_P_MIPI_DSI0_I2C0_SCL 116 /*!< MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */
+#define SC_P_MIPI_DSI0_I2C0_SDA 117 /*!< MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */
+#define SC_P_MIPI_DSI0_GPIO0_00 118 /*!< MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */
+#define SC_P_MIPI_DSI0_GPIO0_01 119 /*!< MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */
+#define SC_P_MIPI_DSI1_I2C0_SCL 120 /*!< MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */
+#define SC_P_MIPI_DSI1_I2C0_SDA 121 /*!< MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */
+#define SC_P_MIPI_DSI1_GPIO0_00 122 /*!< MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */
+#define SC_P_MIPI_DSI1_GPIO0_01 123 /*!< MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 /*!< */
+#define SC_P_JTAG_TRST_B 125 /*!< SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */
+#define SC_P_PMIC_I2C_SCL 126 /*!< SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */
+#define SC_P_PMIC_I2C_SDA 127 /*!< SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */
+#define SC_P_PMIC_INT_B 128 /*!< SCU.DSC.PMIC_INT_B */
+#define SC_P_SCU_GPIO0_00 129 /*!< SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */
+#define SC_P_SCU_GPIO0_01 130 /*!< SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */
+#define SC_P_SCU_PMIC_STANDBY 131 /*!< SCU.DSC.PMIC_STANDBY */
+#define SC_P_SCU_BOOT_MODE0 132 /*!< SCU.DSC.BOOT_MODE0 */
+#define SC_P_SCU_BOOT_MODE1 133 /*!< SCU.DSC.BOOT_MODE1 */
+#define SC_P_SCU_BOOT_MODE2 134 /*!< SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */
+#define SC_P_SCU_BOOT_MODE3 135 /*!< SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */
+#define SC_P_CSI_D00 136 /*!< CI_PI.D02, ADMA.SAI0.RXC */
+#define SC_P_CSI_D01 137 /*!< CI_PI.D03, ADMA.SAI0.RXD */
+#define SC_P_CSI_D02 138 /*!< CI_PI.D04, ADMA.SAI0.RXFS */
+#define SC_P_CSI_D03 139 /*!< CI_PI.D05, ADMA.SAI2.RXC */
+#define SC_P_CSI_D04 140 /*!< CI_PI.D06, ADMA.SAI2.RXD */
+#define SC_P_CSI_D05 141 /*!< CI_PI.D07, ADMA.SAI2.RXFS */
+#define SC_P_CSI_D06 142 /*!< CI_PI.D08, ADMA.SAI3.RXC */
+#define SC_P_CSI_D07 143 /*!< CI_PI.D09, ADMA.SAI3.RXD */
+#define SC_P_CSI_HSYNC 144 /*!< CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */
+#define SC_P_CSI_VSYNC 145 /*!< CI_PI.VSYNC, CI_PI.D01 */
+#define SC_P_CSI_PCLK 146 /*!< CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */
+#define SC_P_CSI_MCLK 147 /*!< CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */
+#define SC_P_CSI_EN 148 /*!< CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */
+#define SC_P_CSI_RESET 149 /*!< CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 /*!< */
+#define SC_P_MIPI_CSI0_MCLK_OUT 151 /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */
+#define SC_P_MIPI_CSI0_I2C0_SCL 152 /*!< MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */
+#define SC_P_MIPI_CSI0_I2C0_SDA 153 /*!< MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */
+#define SC_P_MIPI_CSI0_GPIO0_01 154 /*!< MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */
+#define SC_P_MIPI_CSI0_GPIO0_00 155 /*!< MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */
+#define SC_P_QSPI0A_DATA0 156 /*!< LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */
+#define SC_P_QSPI0A_DATA1 157 /*!< LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */
+#define SC_P_QSPI0A_DATA2 158 /*!< LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */
+#define SC_P_QSPI0A_DATA3 159 /*!< LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */
+#define SC_P_QSPI0A_DQS 160 /*!< LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */
+#define SC_P_QSPI0A_SS0_B 161 /*!< LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */
+#define SC_P_QSPI0A_SS1_B 162 /*!< LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */
+#define SC_P_QSPI0A_SCLK 163 /*!< LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 /*!< */
+#define SC_P_QSPI0B_SCLK 165 /*!< LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */
+#define SC_P_QSPI0B_DATA0 166 /*!< LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */
+#define SC_P_QSPI0B_DATA1 167 /*!< LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */
+#define SC_P_QSPI0B_DATA2 168 /*!< LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */
+#define SC_P_QSPI0B_DATA3 169 /*!< LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */
+#define SC_P_QSPI0B_DQS 170 /*!< LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */
+#define SC_P_QSPI0B_SS0_B 171 /*!< LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */
+#define SC_P_QSPI0B_SS1_B 172 /*!< LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 /*!< */
+/*@}*/
+
+#endif /* _SC_PADS_H */
+
+++ /dev/null
-/*
- * Copyright 2017 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*!
- * Header file used to configure SoC pin list.
- */
-
-#ifndef _SC_PINS_H
-#define _SC_PINS_H
-
-/* Includes */
-
-/* Defines */
-
-#define SC_P_ALL UINT16_MAX /*!< All pins */
-
-/*!
- * @name Pin Definitions
- */
-/*@{*/
-#define SC_P_PCIE_CTRL0_PERST_B 0 /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */
-#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */
-#define SC_P_PCIE_CTRL0_WAKE_B 2 /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /*!< */
-#define SC_P_USB_SS3_TC0 4 /*!< ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */
-#define SC_P_USB_SS3_TC1 5 /*!< ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
-#define SC_P_USB_SS3_TC2 6 /*!< ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */
-#define SC_P_USB_SS3_TC3 7 /*!< ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
-#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 /*!< */
-#define SC_P_EMMC0_CLK 9 /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */
-#define SC_P_EMMC0_CMD 10 /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */
-#define SC_P_EMMC0_DATA0 11 /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */
-#define SC_P_EMMC0_DATA1 12 /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */
-#define SC_P_EMMC0_DATA2 13 /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */
-#define SC_P_EMMC0_DATA3 14 /*!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 /*!< */
-#define SC_P_EMMC0_DATA4 16 /*!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */
-#define SC_P_EMMC0_DATA5 17 /*!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */
-#define SC_P_EMMC0_DATA6 18 /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */
-#define SC_P_EMMC0_DATA7 19 /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */
-#define SC_P_EMMC0_STROBE 20 /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */
-#define SC_P_EMMC0_RESET_B 21 /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 /*!< */
-#define SC_P_USDHC1_RESET_B 23 /*!< CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */
-#define SC_P_USDHC1_VSELECT 24 /*!< CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */
-#define SC_P_CTL_NAND_RE_P_N 25 /*!< */
-#define SC_P_USDHC1_WP 26 /*!< CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */
-#define SC_P_USDHC1_CD_B 27 /*!< CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */
-#define SC_P_CTL_NAND_DQS_P_N 28 /*!< */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 /*!< */
-#define SC_P_USDHC1_CLK 30 /*!< CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */
-#define SC_P_USDHC1_CMD 31 /*!< CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */
-#define SC_P_USDHC1_DATA0 32 /*!< CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */
-#define SC_P_USDHC1_DATA1 33 /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */
-#define SC_P_USDHC1_DATA2 34 /*!< CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */
-#define SC_P_USDHC1_DATA3 35 /*!< CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 /*!< */
-#define SC_P_ENET0_RGMII_TXC 37 /*!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */
-#define SC_P_ENET0_RGMII_TX_CTL 38 /*!< CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */
-#define SC_P_ENET0_RGMII_TXD0 39 /*!< CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */
-#define SC_P_ENET0_RGMII_TXD1 40 /*!< CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */
-#define SC_P_ENET0_RGMII_TXD2 41 /*!< CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */
-#define SC_P_ENET0_RGMII_TXD3 42 /*!< CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 /*!< */
-#define SC_P_ENET0_RGMII_RXC 44 /*!< CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */
-#define SC_P_ENET0_RGMII_RX_CTL 45 /*!< CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */
-#define SC_P_ENET0_RGMII_RXD0 46 /*!< CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */
-#define SC_P_ENET0_RGMII_RXD1 47 /*!< CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */
-#define SC_P_ENET0_RGMII_RXD2 48 /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */
-#define SC_P_ENET0_RGMII_RXD3 49 /*!< CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 /*!< */
-#define SC_P_ENET0_REFCLK_125M_25M 51 /*!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */
-#define SC_P_ENET0_MDIO 52 /*!< CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */
-#define SC_P_ENET0_MDC 53 /*!< CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 /*!< */
-#define SC_P_ESAI0_FSR 55 /*!< ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */
-#define SC_P_ESAI0_FST 56 /*!< ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */
-#define SC_P_ESAI0_SCKR 57 /*!< ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */
-#define SC_P_ESAI0_SCKT 58 /*!< ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */
-#define SC_P_ESAI0_TX0 59 /*!< ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */
-#define SC_P_ESAI0_TX1 60 /*!< ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */
-#define SC_P_ESAI0_TX2_RX3 61 /*!< ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */
-#define SC_P_ESAI0_TX3_RX2 62 /*!< ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */
-#define SC_P_ESAI0_TX4_RX1 63 /*!< ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */
-#define SC_P_ESAI0_TX5_RX0 64 /*!< ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */
-#define SC_P_SPDIF0_RX 65 /*!< ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */
-#define SC_P_SPDIF0_TX 66 /*!< ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */
-#define SC_P_SPDIF0_EXT_CLK 67 /*!< ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 /*!< */
-#define SC_P_SPI3_SCK 69 /*!< ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */
-#define SC_P_SPI3_SDO 70 /*!< ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */
-#define SC_P_SPI3_SDI 71 /*!< ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */
-#define SC_P_SPI3_CS0 72 /*!< ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */
-#define SC_P_SPI3_CS1 73 /*!< ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */
-#define SC_P_MCLK_IN1 74 /*!< ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */
-#define SC_P_MCLK_IN0 75 /*!< ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */
-#define SC_P_MCLK_OUT0 76 /*!< ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */
-#define SC_P_UART1_TX 77 /*!< ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */
-#define SC_P_UART1_RX 78 /*!< ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */
-#define SC_P_UART1_RTS_B 79 /*!< ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */
-#define SC_P_UART1_CTS_B 80 /*!< ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 /*!< */
-#define SC_P_SAI0_TXD 82 /*!< ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */
-#define SC_P_SAI0_TXC 83 /*!< ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */
-#define SC_P_SAI0_RXD 84 /*!< ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */
-#define SC_P_SAI0_TXFS 85 /*!< ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */
-#define SC_P_SAI1_RXD 86 /*!< ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */
-#define SC_P_SAI1_RXC 87 /*!< ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */
-#define SC_P_SAI1_RXFS 88 /*!< ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */
-#define SC_P_SPI2_CS0 89 /*!< ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */
-#define SC_P_SPI2_SDO 90 /*!< ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */
-#define SC_P_SPI2_SDI 91 /*!< ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */
-#define SC_P_SPI2_SCK 92 /*!< ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */
-#define SC_P_SPI0_SCK 93 /*!< ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */
-#define SC_P_SPI0_SDI 94 /*!< ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */
-#define SC_P_SPI0_SDO 95 /*!< ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */
-#define SC_P_SPI0_CS1 96 /*!< ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */
-#define SC_P_SPI0_CS0 97 /*!< ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 /*!< */
-#define SC_P_ADC_IN1 99 /*!< ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */
-#define SC_P_ADC_IN0 100 /*!< ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */
-#define SC_P_ADC_IN3 101 /*!< ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */
-#define SC_P_ADC_IN2 102 /*!< ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */
-#define SC_P_ADC_IN5 103 /*!< ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */
-#define SC_P_ADC_IN4 104 /*!< ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */
-#define SC_P_FLEXCAN0_RX 105 /*!< ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */
-#define SC_P_FLEXCAN0_TX 106 /*!< ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */
-#define SC_P_FLEXCAN1_RX 107 /*!< ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */
-#define SC_P_FLEXCAN1_TX 108 /*!< ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */
-#define SC_P_FLEXCAN2_RX 109 /*!< ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */
-#define SC_P_FLEXCAN2_TX 110 /*!< ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */
-#define SC_P_UART0_RX 111 /*!< ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, LSIO.GPIO1.IO21 */
-#define SC_P_UART0_TX 112 /*!< ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, LSIO.GPIO1.IO22 */
-#define SC_P_UART2_TX 113 /*!< ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */
-#define SC_P_UART2_RX 114 /*!< ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 /*!< */
-#define SC_P_MIPI_DSI0_I2C0_SCL 116 /*!< MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */
-#define SC_P_MIPI_DSI0_I2C0_SDA 117 /*!< MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */
-#define SC_P_MIPI_DSI0_GPIO0_00 118 /*!< MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */
-#define SC_P_MIPI_DSI0_GPIO0_01 119 /*!< MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */
-#define SC_P_MIPI_DSI1_I2C0_SCL 120 /*!< MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */
-#define SC_P_MIPI_DSI1_I2C0_SDA 121 /*!< MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */
-#define SC_P_MIPI_DSI1_GPIO0_00 122 /*!< MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */
-#define SC_P_MIPI_DSI1_GPIO0_01 123 /*!< MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 /*!< */
-#define SC_P_JTAG_TRST_B 125 /*!< SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */
-#define SC_P_PMIC_I2C_SCL 126 /*!< SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */
-#define SC_P_PMIC_I2C_SDA 127 /*!< SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */
-#define SC_P_PMIC_INT_B 128 /*!< SCU.DSC.PMIC_INT_B */
-#define SC_P_SCU_GPIO0_00 129 /*!< SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */
-#define SC_P_SCU_GPIO0_01 130 /*!< SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */
-#define SC_P_SCU_PMIC_STANDBY 131 /*!< SCU.DSC.PMIC_STANDBY */
-#define SC_P_SCU_BOOT_MODE0 132 /*!< SCU.DSC.BOOT_MODE0 */
-#define SC_P_SCU_BOOT_MODE1 133 /*!< SCU.DSC.BOOT_MODE1 */
-#define SC_P_SCU_BOOT_MODE2 134 /*!< SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */
-#define SC_P_SCU_BOOT_MODE3 135 /*!< SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */
-#define SC_P_CSI_D00 136 /*!< CI_PI.D02, ADMA.SAI0.RXC */
-#define SC_P_CSI_D01 137 /*!< CI_PI.D03, ADMA.SAI0.RXD */
-#define SC_P_CSI_D02 138 /*!< CI_PI.D04, ADMA.SAI0.RXFS */
-#define SC_P_CSI_D03 139 /*!< CI_PI.D05, ADMA.SAI2.RXC */
-#define SC_P_CSI_D04 140 /*!< CI_PI.D06, ADMA.SAI2.RXD */
-#define SC_P_CSI_D05 141 /*!< CI_PI.D07, ADMA.SAI2.RXFS */
-#define SC_P_CSI_D06 142 /*!< CI_PI.D08, ADMA.SAI3.RXC */
-#define SC_P_CSI_D07 143 /*!< CI_PI.D09, ADMA.SAI3.RXD */
-#define SC_P_CSI_HSYNC 144 /*!< CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */
-#define SC_P_CSI_VSYNC 145 /*!< CI_PI.VSYNC, CI_PI.D01 */
-#define SC_P_CSI_PCLK 146 /*!< CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */
-#define SC_P_CSI_MCLK 147 /*!< CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */
-#define SC_P_CSI_EN 148 /*!< CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */
-#define SC_P_CSI_RESET 149 /*!< CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 /*!< */
-#define SC_P_MIPI_CSI0_MCLK_OUT 151 /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */
-#define SC_P_MIPI_CSI0_I2C0_SCL 152 /*!< MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */
-#define SC_P_MIPI_CSI0_I2C0_SDA 153 /*!< MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */
-#define SC_P_MIPI_CSI0_GPIO0_01 154 /*!< MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */
-#define SC_P_MIPI_CSI0_GPIO0_00 155 /*!< MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */
-#define SC_P_QSPI0A_DATA0 156 /*!< LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */
-#define SC_P_QSPI0A_DATA1 157 /*!< LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */
-#define SC_P_QSPI0A_DATA2 158 /*!< LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */
-#define SC_P_QSPI0A_DATA3 159 /*!< LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */
-#define SC_P_QSPI0A_DQS 160 /*!< LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */
-#define SC_P_QSPI0A_SS0_B 161 /*!< LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */
-#define SC_P_QSPI0A_SS1_B 162 /*!< LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */
-#define SC_P_QSPI0A_SCLK 163 /*!< LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 /*!< */
-#define SC_P_QSPI0B_SCLK 165 /*!< LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */
-#define SC_P_QSPI0B_DATA0 166 /*!< LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */
-#define SC_P_QSPI0B_DATA1 167 /*!< LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */
-#define SC_P_QSPI0B_DATA2 168 /*!< LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */
-#define SC_P_QSPI0B_DATA3 169 /*!< LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */
-#define SC_P_QSPI0B_DQS 170 /*!< LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */
-#define SC_P_QSPI0B_SS0_B 171 /*!< LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */
-#define SC_P_QSPI0B_SS1_B 172 /*!< LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 /*!< */
-/*@}*/
-
-#endif /* _SC_PINS_H */
-
#define RPC_SVC(MSG) ((MSG)->svc)
#define RPC_FUNC(MSG) ((MSG)->func)
#define RPC_R8(MSG) ((MSG)->func)
-#define RPC_D32(MSG, IDX) ((MSG)->DATA.d32[IDX / 4])
-#define RPC_F32(MSG, IDX) ((MSG)->DATA.f32[IDX / 4])
-#define RPC_D16(MSG, IDX) ((MSG)->DATA.d16[IDX / 2])
-#define RPC_D8(MSG, IDX) ((MSG)->DATA.d8[IDX])
+#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[IDX / 4])
+#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[IDX / 2])
+#define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[IDX])
+#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[IDX / 4])
+#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[IDX / 2])
+#define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[IDX])
/* Types */
uint8_t func;
union
{
- uint32_t d32[(SC_RPC_MAX_MSG - 1)];
- uint16_t d16[(SC_RPC_MAX_MSG - 1) * 2];
- uint8_t d8[(SC_RPC_MAX_MSG - 1) * 4];
+ int32_t i32[(SC_RPC_MAX_MSG - 1)];
+ int16_t i16[(SC_RPC_MAX_MSG - 1) * 2];
+ int8_t i8[(SC_RPC_MAX_MSG - 1) * 4];
+ uint32_t u32[(SC_RPC_MAX_MSG - 1)];
+ uint16_t u16[(SC_RPC_MAX_MSG - 1) * 2];
+ uint8_t u8[(SC_RPC_MAX_MSG - 1) * 4];
} DATA;
} sc_rpc_msg_t;
* @param[in,out] msg handle to a message
*
* This function decodes a message, calls macros to translate the
- * resources, pins, addresses, partitions, memory regions, etc. and
+ * resources, pads, addresses, partitions, memory regions, etc. and
* then forwards on to the hypervisors SCFW API.Return results are
* translated back abd placed back into the message to be returned
* to the original API.
SC_MISC_SECO_AUTH_HDMI_RX_FW = 2 /*!< HDMI RX Firmware */
} sc_misc_seco_auth_cmd_t;
+/*!
+ * This type is used report boot status.
+ */
+typedef enum sc_misc_temp_e
+{
+ SC_MISC_TEMP = 0, /*!< Temp sensor */
+ SC_MISC_TEMP_HIGH = 1, /*!< Temp high alarm */
+ SC_MISC_TEMP_LOW = 2 /*!< Temp low alarm */
+} sc_misc_temp_t;
+
/* Functions */
/*!
void sc_misc_debug_out(sc_ipc_t ipc, uint8_t ch);
/*!
- * This function starts/stops emulator waveform capture.
+ * This function starts/stops emulation waveform capture.
*
* @param[in] ipc IPC handle
* @param[in] enable flag to enable/disable capture
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
- * - SC_ERR_UNAVAILABLE if not running on emulator
+ * - SC_ERR_UNAVAILABLE if not running on emulation
*/
sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, bool enable);
void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status);
/*!
- * This function read a given fuse word index.
+ * This function reads a given fuse word index.
*
* @param[in] word fuse word index
- * @param[in] *value fuse read value
+ * @param[out] value fuse read value
*
* @return Returns and error code (SC_ERR_NONE = success).
*
*/
sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val);
+/*!
+ * This function sets a temp sensor alarm.
+ *
+ * @param[in] resource resource with sensor
+ * @param[in] temp alarm to set
+ * @param[in] celsius whole part of temp to set
+ * @param[in] tenths fractional part of temp to set
+ *
+ * @return Returns and error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if parameters invalid
+ */
+sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_misc_temp_t temp, int16_t celsius, int8_t tenths);
+
+/*!
+ * This function gets a temp sensor value.
+ *
+ * @param[in] resource resource with sensor
+ * @param[in] temp value to get (sensor or alarm)
+ * @param[out] celsius whole part of temp to get
+ * @param[out] tenths fractional part of temp to get
+ *
+ * @return Returns and error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if parameters invalid
+ */
+sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_misc_temp_t temp, int16_t *celsius, int8_t *tenths);
+
/* @} */
#endif /* _SC_MISC_API_H */
*
* Module for the Pad Control (PAD) service.
*
+ * @details
+ *
+ * Pad configuration is managed by SC firmware. The pad configuration
+ * features supported by the SC firmware include:
+ *
+ * - Configuring the mux, input/output connection, and low-power isolation
+ mode.
+ * - Configuring the technology-specific pad setting such as drive strength,
+ * pullup/pulldown, etc.
+ * - Configuring compensation for pad groups with dual voltage capability.
+ *
+ * Pad functions fall into one of three categories. Generic functions are
+ * common to all SoCs and all process technologies. SoC functions are raw
+ * low-level functions. Technology-specific functions are specific to the
+ * process technology.
+ *
+ * The list of pads is SoC specific. Refer to the SoC [Pad List](@ref PADS)
+ * for valid pad values. Note that all pads exist on a die but may or
+ * may not be brought out by the specific package. Mapping of pads to
+ * package pins/balls is documented in the associated Data Sheet. Some pads
+ * may not be brought out because the part (die+package) is defeatured and
+ * some pads may connect to the substrate in the package.
+ *
+ * Some pads (SC_P_COMP_*) that can be specified are not individual pads
+ * but are in fact pad groups. These groups have additional configuration
+ * that can be done using the sc_pad_set_gp_28fdsoi_comp() function. More
+ * info on these can be found in the associated Reference Manual.
+ *
+ * Pads are managed as a resource by the Resource Manager (RM). They have
+ * assigned owners and only the owners can configure the pads.
+ *
* @{
*/
/*!
* This type is used to declare a pad low-power isolation config.
* ISO_LATE is the most common setting. ISO_EARLY is only used when
- * an output pin is directly determined by another input pin. The
+ * an output pad is directly determined by another input pad. The
* other two are only used when SW wants to directly contol isolation.
*/
typedef enum sc_pad_iso_e
} sc_pad_28fdsoi_ps_t;
/*!
- * This type is used to declare a wakeup mode of a pin.
+ * This type is used to declare a wakeup mode of a pad.
*/
typedef enum sc_pad_wakeup_e
{
*/
/*!
- * This function configures the mux settings for a pin. This includes
+ * This function configures the mux settings for a pad. This includes
* the signal mux, pad config, and low-power isolation mode.
*
* @param[in] ipc IPC handle
- * @param[in] pin pin to configure
+ * @param[in] pad pad to configure
* @param[in] mux mux setting
* @param[in] config pad config
* @param[in] iso low-power isolation mode
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
- * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
-sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pin_t pin,
+sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad,
uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso);
/*!
- * This function gets the mux settings for a pin. This includes
+ * This function gets the mux settings for a pad. This includes
* the signal mux, pad config, and low-power isolation mode.
*
* @param[in] ipc IPC handle
- * @param[in] pin pin to query
+ * @param[in] pad pad to query
* @param[out] mux pointer to return mux setting
* @param[out] config pointer to return pad config
* @param[out] iso pointer to return low-power isolation mode
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
- * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
-sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pin_t pin,
+sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad,
uint8_t *mux, sc_pad_config_t *config, sc_pad_iso_t *iso);
/*!
* for bit field details.
*
* @param[in] ipc IPC handle
- * @param[in] pin pin to configure
+ * @param[in] pad pad to configure
* @param[in] ctrl control value to set
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
- * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
-sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pin_t pin, uint32_t ctrl);
+sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl);
/*!
* This function gets the general purpose pad control. This
* for bit field details.
*
* @param[in] ipc IPC handle
- * @param[in] pin pin to query
+ * @param[in] pad pad to query
* @param[out] ctrl pointer to return control value
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
- * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
-sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pin_t pin, uint32_t *ctrl);
+sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl);
/*!
- * This function configures the wakeup mode of the pin.
+ * This function configures the wakeup mode of the pad.
*
* @param[in] ipc IPC handle
- * @param[in] pin pin to configure
+ * @param[in] pad pad to configure
* @param[in] wakeup wakeup to set
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
- * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
-sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pin_t pin,
+sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_wakeup_t wakeup);
/*!
- * This function gets the wakeup mode of a pin.
+ * This function gets the wakeup mode of a pad.
*
* @param[in] ipc IPC handle
- * @param[in] pin pin to query
+ * @param[in] pad pad to query
* @param[out] wakeup pointer to return wakeup
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
- * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
-sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pin_t pin,
+sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_wakeup_t *wakeup);
/*!
* This function configures a pad.
*
* @param[in] ipc IPC handle
- * @param[in] pin pin to configure
+ * @param[in] pad pad to configure
* @param[in] mux mux setting
* @param[in] config pad config
* @param[in] iso low-power isolation mode
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
* @return Returns an error code (SC_ERR_NONE = success).
*
- * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
-sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pin_t pin, uint8_t mux,
+sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux,
sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
sc_pad_wakeup_t wakeup);
* This function gets a pad's config.
*
* @param[in] ipc IPC handle
- * @param[in] pin pin to query
+ * @param[in] pad pad to query
* @param[out] mux pointer to return mux setting
* @param[out] config pointer to return pad config
* @param[out] iso pointer to return low-power isolation mode
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
* @return Returns an error code (SC_ERR_NONE = success).
*
- * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
-sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pin_t pin, uint8_t *mux,
+sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux,
sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl,
sc_pad_wakeup_t *wakeup);
*/
/*!
- * This function configures the settings for a pin. This setting is SoC
+ * This function configures the settings for a pad. This setting is SoC
* specific.
*
* @param[in] ipc IPC handle
- * @param[in] pin pin to configure
+ * @param[in] pad pad to configure
* @param[in] val value to set
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
- * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
-sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pin_t pin, uint32_t val);
+sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, uint32_t val);
/*!
- * This function gets the settings for a pin. This setting is SoC
+ * This function gets the settings for a pad. This setting is SoC
* specific.
*
* @param[in] ipc IPC handle
- * @param[in] pin pin to query
+ * @param[in] pad pad to query
* @param[out] val pointer to return setting
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
- * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
-sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pin_t pin, uint32_t *val);
+sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val);
/* @} */
* This function configures the pad control specific to 28LPP.
*
* @param[in] ipc IPC handle
- * @param[in] pin pin to configure
+ * @param[in] pad pad to configure
* @param[in] dse drive strength
* @param[in] sre slew rate
* @param[in] hys hysteresis
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner,
* - SC_ERR_UNAVAILABLE if process not applicable
*
- * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
-sc_err_t sc_pad_set_gp_28lpp(sc_ipc_t ipc, sc_pin_t pin,
+sc_err_t sc_pad_set_gp_28lpp(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28lpp_dse_t dse, bool sre, bool hys, bool pe,
sc_pad_28lpp_ps_t ps);
* This function gets the pad control specific to 28LPP.
*
* @param[in] ipc IPC handle
- * @param[in] pin pin to query
+ * @param[in] pad pad to query
* @param[out] dse pointer to return drive strength
* @param[out] sre pointer to return slew rate
* @param[out] hys pointer to return hysteresis
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner,
* - SC_ERR_UNAVAILABLE if process not applicable
*
- * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
-sc_err_t sc_pad_get_gp_28lpp(sc_ipc_t ipc, sc_pin_t pin,
+sc_err_t sc_pad_get_gp_28lpp(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28lpp_dse_t *dse, bool *sre, bool *hys, bool *pe,
sc_pad_28lpp_ps_t *ps);
* This function configures the pad control specific to 28FDSOI.
*
* @param[in] ipc IPC handle
- * @param[in] pin pin to configure
+ * @param[in] pad pad to configure
* @param[in] dse drive strength
* @param[in] ps pull select
*
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner,
* - SC_ERR_UNAVAILABLE if process not applicable
*
- * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
-sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pin_t pin,
+sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps);
/*!
* This function gets the pad control specific to 28FDSOI.
*
* @param[in] ipc IPC handle
- * @param[in] pin pin to query
+ * @param[in] pad pad to query
* @param[out] dse pointer to return drive strength
* @param[out] ps pointer to return pull select
*
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner,
* - SC_ERR_UNAVAILABLE if process not applicable
*
- * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
-sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pin_t pin,
+sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps);
/*!
* This function configures the compensation control specific to 28FDSOI.
*
* @param[in] ipc IPC handle
- * @param[in] pin pin to configure
+ * @param[in] pad pad to configure
* @param[in] compen compensation/freeze mode
* @param[in] fastfrz fast freeze
* @param[in] rasrcp compensation code for PMOS
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner,
* - SC_ERR_UNAVAILABLE if process not applicable
*
- * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
-sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pin_t pin,
+sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
uint8_t compen, bool fastfrz, uint8_t rasrcp, uint8_t rasrcn,
bool nasrc_sel);
* This function gets the compensation control specific to 28FDSOI.
*
* @param[in] ipc IPC handle
- * @param[in] pin pin to query
+ * @param[in] pad pad to query
* @param[in] compen pointer to return compensation/freeze mode
* @param[in] fastfrz pointer to return fast freeze
* @param[in] rasrcp pointer to return compensation code for PMOS
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner,
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner,
* - SC_ERR_UNAVAILABLE if process not applicable
*
- * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
-sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pin_t pin,
+sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
uint8_t *compen, bool *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn,
bool *nasrc_sel, bool *compok, uint8_t *nasrc);
*/
sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason);
-
/*!
* This function is used to boot a partition.
*
/*!
* Header file containing the public API for the System Controller (SC)
* Resource Management (RM) function. This includes functions for
- * partitioning resources, pins, and memory regions.
+ * partitioning resources, pads, and memory regions.
*
* @addtogroup RM_SVC (SVC) Resource Management Service
*
* - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
* - SC_ERR_LOCKED if \a pt or caller's partition is locked
*
- * All resources, memory regions, and pins are assigned to the caller/parent.
+ * All resources, memory regions, and pads are assigned to the caller/parent.
* The partition watchdog is disabled (even if locked). DID is freed.
*/
sc_err_t sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt);
* - SC_PARM if \a pt out of range,
* - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt
*
- * If a partition is locked it cannot be freed, have resources/pins assigned
+ * If a partition is locked it cannot be freed, have resources/pads assigned
* to/from it, memory regions created/assigned, DID changed, or parent changed.
*/
sc_err_t sc_rm_partition_lock(sc_ipc_t ipc, sc_rm_pt_t pt);
sc_rm_pt_t pt_parent);
/*!
- * This function moves all movable resources/pins owned by a source partition
+ * This function moves all movable resources/pads owned by a source partition
* to a destination partition. It can be used to more quickly set up a new
* partition if a majority of the caller's resources are to be moved to a
* new partition.
* @param[in] pt_dst handle of partition to which resources should be
* moved to
* @param[in] move_rsrc boolean to indicate if resources should be moved
- * @param[in] move_pins boolean to indicate if pins should be moved
+ * @param[in] move_pads boolean to indicate if pads should be moved
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* - SC_ERR_LOCKED if either partition is locked
*/
sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst,
- bool move_rsrc, bool move_pins);
+ bool move_rsrc, bool move_pads);
/* @} */
/* @} */
/*!
- * @name Pin Functions
+ * @name Pad Functions
* @{
*/
/*!
- * This function assigns ownership of a pin to a partition.
+ * This function assigns ownership of a pad to a partition.
*
* @param[in] ipc IPC handle
- * @param[in] pt handle of partition to which pin should
+ * @param[in] pt handle of partition to which pad should
* be assigned
- * @param[in] pin pin to assign
+ * @param[in] pad pad to assign
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_NOACCESS if caller's partition is restricted,
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner or parent
+ * - SC_ERR_NOACCESS if caller's partition is not the pad owner or parent
* of the owner,
* - SC_ERR_LOCKED if the owning partition or \a pt is locked
*/
-sc_err_t sc_rm_assign_pin(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pin_t pin);
+sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad);
/*!
- * This function flags pins as movable or not.
+ * This function flags pads as movable or not.
*
* @param[in] ipc IPC handle
- * @param[in] pin_fst first pin for which flag should be set
- * @param[in] pin_lst last pin for which flag should be set
+ * @param[in] pad_fst first pad for which flag should be set
+ * @param[in] pad_lst last pad for which flag should be set
* @param[in] movable movable flag (true) is movable
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
- * - SC_PARM if pins are out of range,
- * - SC_ERR_NOACCESS if caller's partition is not a parent of a pin owner,
+ * - SC_PARM if pads are out of range,
+ * - SC_ERR_NOACCESS if caller's partition is not a parent of a pad owner,
* - SC_ERR_LOCKED if the owning partition is locked
*
- * This function is used to determine the set of pins that will be
- * moved using the sc_rm_move_all() function. All pins are movable
+ * This function is used to determine the set of pads that will be
+ * moved using the sc_rm_move_all() function. All pads are movable
* by default so this function is normally used to prevent a set of
- * pins from moving.
+ * pads from moving.
*/
-sc_err_t sc_rm_set_pin_movable(sc_ipc_t ipc, sc_pin_t pin_fst,
- sc_pin_t pin_lst, bool movable);
+sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst,
+ sc_pad_t pad_lst, bool movable);
/*!
- * This function gets ownership status of a pin.
+ * This function gets ownership status of a pad.
*
* @param[in] ipc IPC handle
- * @param[in] pin pin to check
+ * @param[in] pad pad to check
*
- * @return Returns a boolean (true if caller's partition owns the pin).
+ * @return Returns a boolean (true if caller's partition owns the pad).
*
- * If \a pin is out of range then false is returned.
+ * If \a pad is out of range then false is returned.
*/
-bool sc_rm_is_pin_owned(sc_ipc_t ipc, sc_pin_t pin);
+bool sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad);
/* @} */
#define SC_20MHZ 20000000 /*!< 20MHz */
#define SC_25MHZ 25000000 /*!< 25MHz */
#define SC_40MHZ 40000000 /*!< 40MHz */
+#define SC_45MHZ 45000000 /*!< 45MHz */
#define SC_50MHZ 50000000 /*!< 50MHz */
#define SC_60MHZ 60000000 /*!< 60MHz */
#define SC_66MHZ 66666666 /*!< 66MHz */
+#define SC_74MHZ 74250000 /*!< 74.25MHz */
#define SC_80MHZ 80000000 /*!< 80MHz */
#define SC_83MHZ 83333333 /*!< 83MHz */
+#define SC_84MHZ 84375000 /*!< 84.37MHz */
#define SC_100MHZ 100000000 /*!< 100MHz */
#define SC_125MHZ 125000000 /*!< 125MHz */
#define SC_133MHZ 133333333 /*!< 133MHz */
+#define SC_135MHZ 135000000 /*!< 135MHz */
#define SC_150MHZ 150000000 /*!< 150MHz */
#define SC_160MHZ 160000000 /*!< 160MHz */
#define SC_166MHZ 166666666 /*!< 160MHz */
#define SC_375MHZ 375000000 /*!< 375MHz */
#define SC_400MHZ 400000000 /*!< 400MHz */
#define SC_500MHZ 500000000 /*!< 500MHz */
+#define SC_594MHZ 594000000 /*!< 594MHz */
#define SC_650MHZ 650000000 /*!< 650MHz */
#define SC_667MHZ 666666667 /*!< 667MHz */
+#define SC_675MHZ 675000000 /*!< 675MHz */
#define SC_700MHZ 700000000 /*!< 700MHz */
#define SC_720MHZ 720000000 /*!< 720MHz */
#define SC_750MHZ 750000000 /*!< 750MHz */
/*@}*/
#define SC_R_ALL UINT16_MAX /*!< All resources */
-#define SC_P_ALL UINT16_MAX /*!< All pins */
+#define SC_P_ALL UINT16_MAX /*!< All pads */
/*!
* This type is used to store a system (full-size) address.
SC_R_CSI_1_PWM_0 = 405,
SC_R_CSI_1_I2C_0 = 406,
SC_R_HDMI = 407,
- SC_R_HDMI_BYPASS = 408,
+ SC_R_HDMI_I2S = 408,
SC_R_HDMI_I2C_0 = 409,
- SC_R_AUDIO_PLL_2 = 410,
+ SC_R_HDMI_PLL_0 = 410,
SC_R_HDMI_RX = 411,
SC_R_HDMI_RX_BYPASS = 412,
SC_R_HDMI_RX_I2C_0 = 413,
SC_R_CAAM_JR0_OUT = 520,
SC_R_PMIC_2 = 521,
SC_R_DBLOGIC = 522,
+ SC_R_HDMI_PLL_1 = 523,
SC_R_LAST
} sc_rsrc_t;
SC_C_MIPI_RESET = 35,
SC_C_DUAL_MODE = 36,
SC_C_VOLTAGE = 37,
+ SC_C_PXL_LINK_SEL = 38,
SC_C_LAST
} sc_ctrl_t;
/*!
- * This type is used to indicate a pin. Valid values are SoC specific.
+ * This type is used to indicate a pad. Valid values are SoC specific.
*
- * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
-typedef uint16_t sc_pin_t;
+typedef uint16_t sc_pad_t;
/* Extra documentation of standard types */
projects / u-boot.git / commitdiff