MLK-16583 ARM64: dts: imx8qm/qxp: mek: add enet2 for base board

Add enet2 for MEK base board.

BuildInfo:
 - SCFW d0458f9f, IMX-MKIMAGE 1c6fc7d8, ATF a438801
 - U-Boot 2017.03-00042-g543559e

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 63217d2..00f1a30 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -16,6 +16,7 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QM) += fsl-imx8qm-lpddr4-arm2.dtb \
                                 fsl-imx8qm-lpddr4-arm2-usb3.dtb
 dtb-$(CONFIG_ARCH_FSL_IMX8QXP) += fsl-imx8qxp-lpddr4-arm2.dtb \
                                  fsl-imx8qxp-mek.dtb \
+                                 fsl-imx8qxp-mek-enet2.dtb \
                                  fsl-imx8qxp-mek-lvds0-it6263.dtb \
                                  fsl-imx8qxp-mek-lvds1-it6263.dtb \
                                  fsl-imx8qxp-mek-lvds0-lvds1-it6263.dtb \

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
index b3cab81..8f3584b 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
@@ -89,6 +89,23 @@
                        >;
                };
 
+               pinctrl_fec2: fec2grp {
+                       fsl,pins = <
+                               SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000048
+                               SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC       0x06000048
+                               SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0     0x06000048
+                               SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1     0x06000048
+                               SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2     0x06000048
+                               SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3     0x06000048
+                               SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC       0x06000048
+                               SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000048
+                               SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0     0x06000048
+                               SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1     0x06000048
+                               SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2     0x06000048
+                               SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3     0x06000048
+                       >;
+               };
+
                pinctrl_lpuart0: lpuart0grp {
                        fsl,pins = <
                                SC_P_UART0_RX_DMA_UART0_RX              0x06000020
@@ -302,6 +319,15 @@
        };
 };
 
+&fec2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec2>;
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethphy1>;
+       fsl,magic-packet;
+       status = "okay";
+};
+
 &lpuart0 { /* console */
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_lpuart0>;

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-enet2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-enet2.dts
new file mode 100644 (file)
index 0000000..e0ba4d4
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-enet2.dts
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "fsl-imx8qxp-mek.dts"
+
+&esai0 {
+       status = "disabled";
+};
+
+&fec2 {
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts
index b813bba..bd64707 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts
@@ -276,6 +276,23 @@
                        >;
                };
 
+               pinctrl_fec2: fec2grp {
+                       fsl,pins = <
+                               SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL         0x06000048
+                               SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC             0x06000048
+                               SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0        0x06000048
+                               SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1        0x06000048
+                               SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2            0x06000048
+                               SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3           0x06000048
+                               SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC             0x06000048
+                               SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL          0x06000048
+                               SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0            0x06000048
+                               SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1        0x06000048
+                               SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2        0x06000048
+                               SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3            0x06000048
+                       >;
+               };
+
                pinctrl_flexcan1: flexcan0grp {
                        fsl,pins = <
                                SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX               0x21
@@ -523,6 +540,15 @@
        };
 };
 
+&fec2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec2>;
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethphy1>;
+       fsl,magic-packet;
+       status = "disabled";
+};
+
 &flexcan1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_flexcan1>;