MLK-11602 arm: imx: set imx6qdl eim_slow clk to 135Mhz

weim nor read performance drop 32% compared with L3.10.53_1.1.0_GA because
eim_slow clk rate drops. This patch set the eim_slow clk to 135Mhz to improve
the performance.

Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Gao Pan <b54642@freescale.com>

diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index c81c727..071cd8d 100644 (file)
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -896,6 +896,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]);
        clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]);
 
+       imx_clk_set_parent(clk[IMX6QDL_CLK_AXI_ALT_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_AXI_SEL], clk[IMX6QDL_CLK_AXI_ALT_SEL]);
+
+
        /*
         * The gpmi needs 100MHz frequency in the EDO/Sync mode,
         * We can not get the 100MHz from the pll2_pfd0_352m.
@@ -952,8 +956,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        if (IS_ENABLED(CONFIG_PCI_IMX6))
                clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
 
-       /* set eim_slow to 132Mhz */
-       imx_clk_set_rate(clk[IMX6QDL_CLK_EIM_SLOW], 132000000);
+       /* set eim_slow to 135Mhz */
+       imx_clk_set_rate(clk[IMX6QDL_CLK_EIM_SLOW], 135000000);
 
        /*
         * Enable clocks only after both parent and rate are all initialized