MLK-21849-6 DTS: imx8qm_arm2: Update DTS file for supporting SPL
authorYe Li <ye.li@nxp.com>
Fri, 26 Apr 2019 09:25:55 +0000 (02:25 -0700)
committerYe Li <ye.li@nxp.com>
Fri, 24 May 2019 11:28:13 +0000 (04:28 -0700)
Add -u-boot.dtsi for LPDDR4 ARM2 board DTS file and DDR4 ARM2 board DTS file.

In the board level -u-boot.dtsi, add the "u-boot,dm-spl" for SPL boot relative
device nodes and its pinconfig, regulator and power domain nodes.

Signed-off-by: Ye Li <ye.li@nxp.com>
arch/arm/dts/fsl-imx8qm-ddr4-arm2-u-boot.dtsi [new file with mode: 0644]
arch/arm/dts/fsl-imx8qm-ddr4-arm2.dts
arch/arm/dts/fsl-imx8qm-lpddr4-arm2-u-boot.dtsi [new file with mode: 0644]
arch/arm/dts/fsl-imx8qm-lpddr4-arm2.dts

diff --git a/arch/arm/dts/fsl-imx8qm-ddr4-arm2-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-ddr4-arm2-u-boot.dtsi
new file mode 100644 (file)
index 0000000..53029a5
--- /dev/null
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+&{/imx8qm-pm} {
+
+       u-boot,dm-spl;
+};
+
+&mu {
+       u-boot,dm-spl;
+};
+
+&clk {
+       u-boot,dm-spl;
+};
+
+&iomuxc {
+       u-boot,dm-spl;
+};
+
+&{/mu@5d1c0000/iomuxc/imx8qm-arm2} {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3_gpio {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3_100mhz {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3_200mhz {
+       u-boot,dm-spl;
+};
+
+&pinctrl_lpuart0 {
+       u-boot,dm-spl;
+};
+
+&pd_lsio {
+       u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+       u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+       u-boot,dm-spl;
+};
+
+&pd_conn {
+       u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+       u-boot,dm-spl;
+};
+
+&gpio2 {
+       u-boot,dm-spl;
+};
+
+&gpio4 {
+       u-boot,dm-spl;
+};
+
+
+&lpuart0 {
+       u-boot,dm-spl;
+};
+
+&usdhc3 {
+       u-boot,dm-spl;
+};
index 9ecbe2e..eb2f84c 100644 (file)
@@ -7,7 +7,6 @@
 /dts-v1/;
 
 #include "fsl-imx8qm.dtsi"
-#include "fsl-imx8qm-u-boot.dtsi"
 
 / {
        model = "Freescale i.MX8QM ARM2";
diff --git a/arch/arm/dts/fsl-imx8qm-lpddr4-arm2-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-lpddr4-arm2-u-boot.dtsi
new file mode 100644 (file)
index 0000000..d7ed739
--- /dev/null
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+&{/imx8qm-pm} {
+
+       u-boot,dm-spl;
+};
+
+&mu {
+       u-boot,dm-spl;
+};
+
+&clk {
+       u-boot,dm-spl;
+};
+
+&iomuxc {
+       u-boot,dm-spl;
+};
+
+&{/regulators} {
+       u-boot,dm-spl;
+};
+
+&reg_usdhc2_vmmc {
+       u-boot,dm-spl;
+};
+
+&{/mu@5d1c0000/iomuxc/imx8qm-arm2} {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_100mhz {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_200mhz {
+       u-boot,dm-spl;
+};
+
+&pinctrl_lpuart0 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_100mhz {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_200mhz {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_flexspi0 {
+       u-boot,dm-spl;
+};
+
+&pd_lsio {
+       u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+       u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+       u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+       u-boot,dm-spl;
+};
+
+&pd_lsio_flexspi0 {
+       u-boot,dm-spl;
+};
+
+&pd_conn {
+       u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+       u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+       u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+       u-boot,dm-spl;
+};
+
+&gpio2 {
+       u-boot,dm-spl;
+};
+
+&gpio4 {
+       u-boot,dm-spl;
+};
+
+&gpio5 {
+       u-boot,dm-spl;
+};
+
+&lpuart0 {
+       u-boot,dm-spl;
+};
+
+&usdhc1 {
+       u-boot,dm-spl;
+};
+
+&usdhc2 {
+       u-boot,dm-spl;
+};
+
+&usdhc3 {
+       u-boot,dm-spl;
+};
+
+&flexspi0 {
+       u-boot,dm-spl;
+};
+
+&flash0 {
+       u-boot,dm-spl;
+};
\ No newline at end of file
index c45ae0c..7e41587 100644 (file)
@@ -7,7 +7,6 @@
 /dts-v1/;
 
 #include "fsl-imx8qm.dtsi"
-#include "fsl-imx8qm-u-boot.dtsi"
 
 / {
        model = "Freescale i.MX8QM ARM2";