MLK-14874 ARM: imx7d: Ensure ARM clock only disabled if cpus in same state

GPC will stop ARM clock if both CPUs are in idle and CPU_CLK_ON_LPM is
set in GPC_LPCR_A7_BSC. Make sure that doesn't happen when cpu1 enters
state2 and cpu0 enters state0 because the default arm WFI state is not
marked with CPUIDLE_FLAG_TIMER_STOP and it can result in arch_sys_timer
being stopped unexpectedly.

It is possible to reproduce incorrect behavior by explicitly disabling
other idle states for cpu0/cpu1 and timing how much sleep calls take on
cpu0. Ocassionaly something like "sleep 1" will take 3-4 seconds to
complete.

Make sure that both CPUs are in the same idle state before entering
WAIT.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>

diff --git a/arch/arm/mach-imx/cpuidle-imx7d.c b/arch/arm/mach-imx/cpuidle-imx7d.c
index a6fb28f..21ab5e1 100644 (file)
--- a/arch/arm/mach-imx/cpuidle-imx7d.c
+++ b/arch/arm/mach-imx/cpuidle-imx7d.c
@@ -105,10 +105,10 @@ static int imx7d_enter_low_power_idle(struct cpuidle_device *dev,
                atomic_dec(&master_wait);
                imx_gpcv2_set_lpm_mode(WAIT_CLOCKED);
        } else {
-               imx_gpcv2_set_lpm_mode(WAIT_UNCLOCKED);
                cpu_pm_enter();
                if (atomic_inc_return(&master_lpi) == num_online_cpus() &&
                        cpuidle_pm_info->last_cpu == -1) {
+                       imx_gpcv2_set_lpm_mode(WAIT_UNCLOCKED);
                        imx_gpcv2_set_cpu_power_gate_in_idle(true);
                        cpu_cluster_pm_enter();