iwlwifi: pcie: gen3: indicate 8k/12k RB size to device
authorJohannes Berg <johannes.berg@intel.com>
Fri, 29 May 2020 06:39:26 +0000 (09:39 +0300)
committerLuca Coelho <luciano.coelho@intel.com>
Fri, 29 May 2020 07:32:22 +0000 (10:32 +0300)
Newer firmware versions will parse a few extra bits in the
context info to be able to determine whether we are using
bigger than 4k RBs, indicate 8k/12k to them if we actually
use those (e.g. for sniffer based on the module parameter).

Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Link: https://lore.kernel.org/r/iwlwifi.20200529092401.f83f994572ca.Ibcfd66c3f9b69e68a53b3b2df8331ffb225db655@changeid
drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h
drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-gen3.c

index ebea991..9d7a048 100644 (file)
@@ -5,7 +5,7 @@
  *
  * GPL LICENSE SUMMARY
  *
- * Copyright(c) 2018 Intel Corporation
+ * Copyright(c) 2018, 2020 Intel Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of version 2 of the GNU General Public License as
@@ -18,7 +18,7 @@
  *
  * BSD LICENSE
  *
- * Copyright(c) 2018 Intel Corporation
+ * Copyright(c) 2018, 2020 Intel Corporation
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -93,6 +93,11 @@ enum iwl_prph_scratch_mtr_format {
  * @IWL_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd.
  *     There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit,
  *     3: 256 bit.
+ * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored
+ *     by older firmware versions, so set IWL_PRPH_SCRATCH_RB_SIZE_4K
+ *     appropriately; use the below values for this.
+ * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size
+ * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size
  */
 enum iwl_prph_scratch_flags {
        IWL_PRPH_SCRATCH_EARLY_DEBUG_EN         = BIT(4),
@@ -103,6 +108,9 @@ enum iwl_prph_scratch_flags {
        IWL_PRPH_SCRATCH_RB_SIZE_4K             = BIT(16),
        IWL_PRPH_SCRATCH_MTR_MODE               = BIT(17),
        IWL_PRPH_SCRATCH_MTR_FORMAT             = BIT(18) | BIT(19),
+       IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK       = 0xf << 20,
+       IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K         = 8 << 20,
+       IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K        = 9 << 20,
 };
 
 /*
index b6a5921..dcd81ee 100644 (file)
@@ -138,9 +138,17 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
        case IWL_AMSDU_2K:
                break;
        case IWL_AMSDU_4K:
+               control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
+               break;
        case IWL_AMSDU_8K:
+               control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
+               /* if firmware supports the ext size, tell it */
+               control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K;
+               break;
        case IWL_AMSDU_12K:
                control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
+               /* if firmware supports the ext size, tell it */
+               control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K;
                break;
        }