int ret;
if (0 == fec_id) {
+ if (check_module_fused(MX6_MODULE_ENET1))
+ return -1;
/*
* Use 50M anatop loopback REF_CLK1 for ENET1,
* clear gpr1[13], set gpr1[17]
return ret;
} else {
+ if (check_module_fused(MX6_MODULE_ENET2))
+ return -1;
+
/* clk from phy, set gpr1[14], clear gpr1[18]*/
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK);
int ret;
if (fec_id == 0) {
+ if (check_module_fused(MX6_MODULE_ENET1))
+ return -1;
+
/*
* Use 50M anatop loopback REF_CLK1 for ENET1,
* clear gpr1[13], set gpr1[17].
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
} else {
+ if (check_module_fused(MX6_MODULE_ENET2))
+ return -1;
+
/*
* Use 50M anatop loopback REF_CLK2 for ENET2,
* clear gpr1[14], set gpr1[18].
#define CONFIG_WAVEFORM_BUF_SIZE 0x400000
#endif
+#define CONFIG_MODULE_FUSE
+#define CONFIG_OF_SYSTEM_SETUP
+
#endif
#define CONFIG_IMX_VIDEO_SKIP
#endif
+#define CONFIG_MODULE_FUSE
+#define CONFIG_OF_SYSTEM_SETUP
+
#endif