u32 get_cpu_rev(void)
{
- /* TODO: */
- return (MXC_CPU_IMX8MQ << 12) | (1 << 4);
+ u32 reg = readl((void __iomem *)DIGPROG);
+ u32 type = (reg >> 16) & 0xff;
+
+ reg &= 0xff;
+
+ if (reg == 0x10) {
+ /* For B0 chip, the DIGPROG is not updated, still TO1.0.
+ * we have to check ROM version further
+ */
+ uint32_t rom_version;
+ rom_version = readl((void __iomem *)0x800);
+ if (rom_version != 0x10) {
+ rom_version = readl((void __iomem *)0x83c);
+ if (rom_version >= 0x20)
+ reg = 0x20;
+ }
+ }
+
+ return (type << 12) | reg;
}
void imx_set_wdog_powerdown(bool enable)
enum boot_device get_boot_device(void)
{
struct bootrom_sw_info **p =
+ is_soc_rev(CHIP_REV_1_0)? (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 :
(struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
enum boot_device boot_dev = SD1_BOOT;
int mmc_get_env_dev(void)
{
struct bootrom_sw_info **p =
+ is_soc_rev(CHIP_REV_1_0)? (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 :
(struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
int devno = (*p)->boot_dev_instance;
u8 boot_type = (*p)->boot_dev_type;
#define MXC_CPU_MX7S 0x71 /* dummy ID */
#define MXC_CPU_MX7D 0x72
#define MXC_CPU_MX7ULP 0x81 /* Temporally hard code */
+#define MXC_CPU_IMX8MQ 0x82
#define MXC_CPU_IMX8QM 0x91 /* dummy ID */
#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
#define MXC_CPU_IMX8DX 0x93 /* dummy ID */
-#define MXC_CPU_IMX8MQ 0xA1 /* dummy ID */
#define MXC_CPU_VF610 0xF6 /* dummy ID */
#define MXC_SOC_MX6 0x60
#define BOOT_TYPE_SPINOR 0x6
#define BOOT_TYPE_USB 0xF
-#define ROM_SW_INFO_ADDR 0x000009e8
+#define ROM_SW_INFO_ADDR 0x00000968
+#define ROM_SW_INFO_ADDR_A0 0x000009e8
struct bootrom_sw_info {
u8 reserved_1;