MLK-17428-9: ARM64: dts: change the clock frequency to support 768kHz

The bit clock for 786KHz, 16bit, 2 channel is 24.576MHz, and the default
divider of SAI is at least 2, so the minimum master clock should be 49MHz.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts
index c3ba8f0..35133c2 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts
@@ -731,7 +731,7 @@
        assigned-clocks = <&clk IMX8MQ_CLK_SAI1_SRC>,
                        <&clk IMX8MQ_CLK_SAI1_DIV>;
        assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
-       assigned-clock-rates = <0>, <24576000>;
+       assigned-clock-rates = <0>, <49152000>;
        status = "okay";
 };
 
@@ -759,7 +759,7 @@
        assigned-clocks = <&clk IMX8MQ_CLK_SAI5_SRC>,
                        <&clk IMX8MQ_CLK_SAI5_DIV>;
        assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
-       assigned-clock-rates = <0>, <24576000>;
+       assigned-clock-rates = <0>, <49152000>;
        fsl,sai-asynchronous;
        status = "okay";
 };