MLK-21849-4 DTS: imx8qm_mek: Update DTS file for supporting SPL
authorYe Li <ye.li@nxp.com>
Fri, 26 Apr 2019 09:17:56 +0000 (02:17 -0700)
committerYe Li <ye.li@nxp.com>
Fri, 24 May 2019 11:28:07 +0000 (04:28 -0700)
Since there are some board leve DTS nodes needing "u-boot,dm-spl", we
have to use -u-boot.dtsi for each board DTS file. So discard the
SOC level -u-boot.dtsi

Add the "u-boot,dm-spl" for SPL boot relative device nodes and its pinconfig,
regulator and power domain nodes.

Signed-off-by: Ye Li <ye.li@nxp.com>
arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi [new file with mode: 0644]
arch/arm/dts/fsl-imx8qm-mek.dts
arch/arm/dts/fsl-imx8qm-u-boot.dtsi [deleted file]

diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
new file mode 100644 (file)
index 0000000..a48a73e
--- /dev/null
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+&{/imx8qm-pm} {
+
+       u-boot,dm-spl;
+};
+
+&mu {
+       u-boot,dm-spl;
+};
+
+&clk {
+       u-boot,dm-spl;
+};
+
+&iomuxc {
+       u-boot,dm-spl;
+};
+
+&{/regulators} {
+       u-boot,dm-spl;
+};
+
+&reg_usdhc2_vmmc {
+       u-boot,dm-spl;
+};
+
+&{/mu@5d1c0000/iomuxc/imx8qm-mek} {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_100mhz {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_200mhz {
+       u-boot,dm-spl;
+};
+
+&pinctrl_lpuart0 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_100mhz {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_200mhz {
+       u-boot,dm-spl;
+};
+
+&pinctrl_flexspi0 {
+       u-boot,dm-spl;
+};
+
+&pd_lsio {
+       u-boot,dm-spl;
+};
+
+&pd_lsio_gpio1 {
+       u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+       u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+       u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+       u-boot,dm-spl;
+};
+
+&pd_lsio_flexspi0 {
+       u-boot,dm-spl;
+};
+
+&pd_conn {
+       u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+       u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+       u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+       u-boot,dm-spl;
+};
+
+&gpio1 {
+       u-boot,dm-spl;
+};
+
+&gpio2 {
+       u-boot,dm-spl;
+};
+
+&gpio4 {
+       u-boot,dm-spl;
+};
+
+&gpio5 {
+       u-boot,dm-spl;
+};
+
+&lpuart0 {
+       u-boot,dm-spl;
+};
+
+&usdhc1 {
+       u-boot,dm-spl;
+};
+
+&usdhc2 {
+       u-boot,dm-spl;
+};
+
+&flexspi0 {
+       u-boot,dm-spl;
+};
+
+&flash0 {
+       u-boot,dm-spl;
+};
\ No newline at end of file
index 22163b9..b04d711 100644 (file)
@@ -15,7 +15,6 @@
 /dts-v1/;
 
 #include "fsl-imx8qm.dtsi"
-#include "fsl-imx8qm-u-boot.dtsi"
 
 / {
        model = "Freescale i.MX8QM MEK";
diff --git a/arch/arm/dts/fsl-imx8qm-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-u-boot.dtsi
deleted file mode 100644 (file)
index 35bb7df..0000000
+++ /dev/null
@@ -1,125 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2018 NXP
- */
-
-&{/imx8qm-pm} {
-
-       u-boot,dm-spl;
-};
-
-&mu {
-       u-boot,dm-spl;
-};
-
-&clk {
-       u-boot,dm-spl;
-};
-
-&iomuxc {
-       u-boot,dm-spl;
-};
-
-&pd_lsio {
-       u-boot,dm-spl;
-};
-
-&pd_lsio_gpio0 {
-       u-boot,dm-spl;
-};
-
-&pd_lsio_gpio1 {
-       u-boot,dm-spl;
-};
-
-&pd_lsio_gpio2 {
-       u-boot,dm-spl;
-};
-
-&pd_lsio_gpio3 {
-       u-boot,dm-spl;
-};
-
-&pd_lsio_gpio4 {
-       u-boot,dm-spl;
-};
-
-&pd_lsio_gpio5 {
-       u-boot,dm-spl;
-};
-
-&pd_lsio_gpio6 {
-       u-boot,dm-spl;
-};
-
-&pd_lsio_gpio7 {
-       u-boot,dm-spl;
-};
-
-&pd_lsio_flexspi0 {
-       u-boot,dm-spl;
-};
-
-&pd_conn {
-       u-boot,dm-spl;
-};
-
-&pd_conn_sdch0 {
-       u-boot,dm-spl;
-};
-
-&pd_conn_sdch1 {
-       u-boot,dm-spl;
-};
-
-&pd_conn_sdch2 {
-       u-boot,dm-spl;
-};
-
-&gpio0 {
-       u-boot,dm-spl;
-};
-
-&gpio1 {
-       u-boot,dm-spl;
-};
-
-&gpio2 {
-       u-boot,dm-spl;
-};
-
-&gpio3 {
-       u-boot,dm-spl;
-};
-
-&gpio4 {
-       u-boot,dm-spl;
-};
-
-&gpio5 {
-       u-boot,dm-spl;
-};
-
-&gpio6 {
-       u-boot,dm-spl;
-};
-
-&gpio7 {
-       u-boot,dm-spl;
-};
-
-&lpuart0 {
-       u-boot,dm-spl;
-};
-
-&usdhc1 {
-       u-boot,dm-spl;
-};
-
-&usdhc2 {
-       u-boot,dm-spl;
-};
-
-&flexspi0 {
-       u-boot,dm-spl;
-};