ARM: dts: uniphier: add reset-names to NAND controller node
authorMasahiro Yamada <yamada.masahiro@socionext.com>
Fri, 28 Feb 2020 12:57:20 +0000 (21:57 +0900)
committerMasahiro Yamada <yamada.masahiro@socionext.com>
Sat, 29 Feb 2020 05:11:36 +0000 (14:11 +0900)
Import Linux commits:

37f3e0096f71 ("ARM: dts: uniphier: add reset-names to NAND controller node")
e98d5023fe1f ("arm64: dts: uniphier: add reset-names to NAND controller node")

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
arch/arm/dts/uniphier-ld11.dtsi
arch/arm/dts/uniphier-ld20.dtsi
arch/arm/dts/uniphier-ld4.dtsi
arch/arm/dts/uniphier-pro4.dtsi
arch/arm/dts/uniphier-pro5.dtsi
arch/arm/dts/uniphier-pxs2.dtsi
arch/arm/dts/uniphier-pxs3.dtsi
arch/arm/dts/uniphier-sld8.dtsi

index b3d44e8..e0737ac 100644 (file)
                        pinctrl-0 = <&pinctrl_nand>;
                        clock-names = "nand", "nand_x", "ecc";
                        clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
-                       resets = <&sys_rst 2>;
+                       reset-names = "nand", "reg";
+                       resets = <&sys_rst 2>, <&sys_rst 2>;
                };
        };
 };
index 5a7bd33..59e4191 100644 (file)
                        pinctrl-0 = <&pinctrl_nand>;
                        clock-names = "nand", "nand_x", "ecc";
                        clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
-                       resets = <&sys_rst 2>;
+                       reset-names = "nand", "reg";
+                       resets = <&sys_rst 2>, <&sys_rst 2>;
                };
        };
 };
index e40407a..1eebc7f 100644 (file)
                        pinctrl-0 = <&pinctrl_nand2cs>;
                        clock-names = "nand", "nand_x", "ecc";
                        clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
-                       resets = <&sys_rst 2>;
+                       reset-names = "nand", "reg";
+                       resets = <&sys_rst 2>, <&sys_rst 2>;
                };
        };
 };
index 7e81260..d006b45 100644 (file)
                        pinctrl-0 = <&pinctrl_nand>;
                        clock-names = "nand", "nand_x", "ecc";
                        clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
-                       resets = <&sys_rst 2>;
+                       reset-names = "nand", "reg";
+                       resets = <&sys_rst 2>, <&sys_rst 2>;
                };
        };
 };
index 05828d7..ba7e224 100644 (file)
                        pinctrl-0 = <&pinctrl_nand2cs>;
                        clock-names = "nand", "nand_x", "ecc";
                        clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
-                       resets = <&sys_rst 2>;
+                       reset-names = "nand", "reg";
+                       resets = <&sys_rst 2>, <&sys_rst 2>;
                };
 
                emmc: mmc@68400000 {
index bf852c2..8d968d3 100644 (file)
                        pinctrl-0 = <&pinctrl_nand2cs>;
                        clock-names = "nand", "nand_x", "ecc";
                        clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
-                       resets = <&sys_rst 2>;
+                       reset-names = "nand", "reg";
+                       resets = <&sys_rst 2>, <&sys_rst 2>;
                };
        };
 };
index f830cef..ed079c1 100644 (file)
                        pinctrl-0 = <&pinctrl_nand>;
                        clock-names = "nand", "nand_x", "ecc";
                        clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
-                       resets = <&sys_rst 2>;
+                       reset-names = "nand", "reg";
+                       resets = <&sys_rst 2>, <&sys_rst 2>;
                };
        };
 };
index 332a4da..393157e 100644 (file)
                        pinctrl-0 = <&pinctrl_nand2cs>;
                        clock-names = "nand", "nand_x", "ecc";
                        clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
-                       resets = <&sys_rst 2>;
+                       reset-names = "nand", "reg";
+                       resets = <&sys_rst 2>, <&sys_rst 2>;
                };
        };
 };