LF-440: arm64: dts: enable fspi on imx8qxp val board

enable fspi on imx8qxp val board

Signed-off-by: Han Xu <han.xu@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts
index 0cd8105..fdde9fc 100755 (executable)
--- a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts
@@ -270,6 +270,19 @@
        status = "okay";
 };
 
+&flexspi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexspi0>;
+       status = "okay";
+
+       mt35xu512aba0:flash@0 {
+               reg = <0>;
+               compatible = "jedec,spi-nor";
+               spi-max-frequency = <133000000>;
+               spi-nor,ddr-quad-read-dummy = <8>;
+       };
+};
+
 &i2c_mipi_csi0 {
        #address-cells = <1>;
        #size-cells = <0>;
@@ -376,6 +389,27 @@
                >;
        };
 
+       pinctrl_flexspi0: flexspi0grp {
+               fsl,pins = <
+                       IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0                  0x06000021
+                       IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1                  0x06000021
+                       IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2                  0x06000021
+                       IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3                  0x06000021
+                       IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS                      0x06000021
+                       IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B                  0x06000021
+                       IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B                  0x06000021
+                       IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK                    0x06000021
+                       IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK                    0x06000021
+                       IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0                  0x06000021
+                       IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1                  0x06000021
+                       IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2                  0x06000021
+                       IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3                  0x06000021
+                       IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS                      0x06000021
+                       IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B                  0x06000021
+                       IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B                  0x06000021
+       >;
+};
+
        pinctrl_lpi2c3: lpi2cgrp {
                fsl,pins = <
                        IMX8QXP_SPI3_CS1_ADMA_I2C3_SCL                          0x06000020