IMX_PINCTRL_PIN(SC_P_EMMC0_DATA7),
IMX_PINCTRL_PIN(SC_P_EMMC0_STROBE),
IMX_PINCTRL_PIN(SC_P_EMMC0_RESET_B),
- IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0),
IMX_PINCTRL_PIN(SC_P_USDHC1_RESET_B),
IMX_PINCTRL_PIN(SC_P_USDHC1_VSELECT),
IMX_PINCTRL_PIN(SC_P_USDHC1_WP),
IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_RXD1),
IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_RXD2),
IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_RXD3),
- IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0),
IMX_PINCTRL_PIN(SC_P_ENET0_REFCLK_125M_25M),
IMX_PINCTRL_PIN(SC_P_ENET0_MDIO),
IMX_PINCTRL_PIN(SC_P_ENET0_MDC),
IMX_PINCTRL_PIN(SC_P_FLEXCAN1_TX),
IMX_PINCTRL_PIN(SC_P_UART0_RX),
IMX_PINCTRL_PIN(SC_P_UART0_TX),
- IMX_PINCTRL_PIN(SC_P_UART0_RTS_B),
- IMX_PINCTRL_PIN(SC_P_UART0_CTS_B),
IMX_PINCTRL_PIN(SC_P_UART1_TX),
IMX_PINCTRL_PIN(SC_P_UART1_RX),
IMX_PINCTRL_PIN(SC_P_UART1_RTS_B),
IMX_PINCTRL_PIN(SC_P_SPI2_SDO),
IMX_PINCTRL_PIN(SC_P_SPI2_SDI),
IMX_PINCTRL_PIN(SC_P_SPI2_CS0),
- IMX_PINCTRL_PIN(SC_P_SPI2_CS1),
IMX_PINCTRL_PIN(SC_P_SAI1_RXC),
IMX_PINCTRL_PIN(SC_P_SAI1_RXD),
IMX_PINCTRL_PIN(SC_P_SAI1_RXFS),
- IMX_PINCTRL_PIN(SC_P_SAI1_TXC),
- IMX_PINCTRL_PIN(SC_P_SAI1_TXD),
- IMX_PINCTRL_PIN(SC_P_SAI1_TXFS),
IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT),
IMX_PINCTRL_PIN(SC_P_ESAI0_FSR),
IMX_PINCTRL_PIN(SC_P_ESAI0_FST),
IMX_PINCTRL_PIN(SC_P_SPI3_CS1),
IMX_PINCTRL_PIN(SC_P_MCLK_IN0),
IMX_PINCTRL_PIN(SC_P_MCLK_OUT0),
- IMX_PINCTRL_PIN(SC_P_FTM0),
IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB),
IMX_PINCTRL_PIN(SC_P_ADC_IN1),
IMX_PINCTRL_PIN(SC_P_ADC_IN0),
IMX_PINCTRL_PIN(SC_P_QSPI0B_DQS),
IMX_PINCTRL_PIN(SC_P_QSPI0B_SS0_B),
IMX_PINCTRL_PIN(SC_P_QSPI0B_SS1_B),
- IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0),
- IMX_PINCTRL_PIN(SC_P_XTALI),
- IMX_PINCTRL_PIN(SC_P_XTALO),
- IMX_PINCTRL_PIN(SC_P_ANA_TEST_OUT_P),
- IMX_PINCTRL_PIN(SC_P_ANA_TEST_OUT_N),
- IMX_PINCTRL_PIN(SC_P_RTC_XTALI),
- IMX_PINCTRL_PIN(SC_P_RTC_XTALO),
- IMX_PINCTRL_PIN(SC_P_PMIC_ON_REQ),
- IMX_PINCTRL_PIN(SC_P_ON_OFF_BUTTON),
};
static struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = {
* This type is used to indicate RPC IRQ function calls.
*/
typedef enum irq_func_e {
- IRQ_FUNC_UNKNOWN, /* Unknown function */
- IRQ_FUNC_ENABLE, /* Index for irq_enable() RPC call */
- IRQ_FUNC_STATUS, /* Index for irq_status() RPC call */
+ IRQ_FUNC_UNKNOWN = 0, /* Unknown function */
+ IRQ_FUNC_ENABLE = 1, /* Index for irq_enable() RPC call */
+ IRQ_FUNC_STATUS = 2, /* Index for irq_status() RPC call */
} irq_func_t;
/* Functions */
* This type is used to indicate RPC MISC function calls.
*/
typedef enum misc_func_e {
- MISC_FUNC_UNKNOWN, /* Unknown function */
- MISC_FUNC_SET_CONTROL, /* Index for misc_set_control() RPC call */
- MISC_FUNC_GET_CONTROL, /* Index for misc_get_control() RPC call */
- MISC_FUNC_SET_ARI, /* Index for misc_set_ari() RPC call */
- MISC_FUNC_SET_MAX_DMA_GROUP, /* Index for misc_set_max_dma_group() RPC call */
- MISC_FUNC_SET_DMA_GROUP, /* Index for misc_set_dma_group() RPC call */
- MISC_FUNC_WAVEFORM_CAPTURE, /* Index for misc_waveform_capture() RPC call */
- MISC_FUNC_BOOT_STATUS, /* Index for misc_boot_status() RPC call */
- MISC_FUNC_SECO_IMAGE_LOAD, /* Index for misc_seco_image_load() RPC call */
- MISC_FUNC_SECO_AUTHENTICATE, /* Index for misc_seco_authenticate() RPC call */
+ MISC_FUNC_UNKNOWN = 0, /* Unknown function */
+ MISC_FUNC_SET_CONTROL = 1, /* Index for misc_set_control() RPC call */
+ MISC_FUNC_GET_CONTROL = 2, /* Index for misc_get_control() RPC call */
+ MISC_FUNC_SET_MAX_DMA_GROUP = 4, /* Index for misc_set_max_dma_group() RPC call */
+ MISC_FUNC_SET_DMA_GROUP = 5, /* Index for misc_set_dma_group() RPC call */
+ MISC_FUNC_SECO_IMAGE_LOAD = 8, /* Index for misc_seco_image_load() RPC call */
+ MISC_FUNC_SECO_AUTHENTICATE = 9, /* Index for misc_seco_authenticate() RPC call */
+ MISC_FUNC_DEBUG_OUT = 10, /* Index for misc_debug_out() RPC call */
+ MISC_FUNC_WAVEFORM_CAPTURE = 6, /* Index for misc_waveform_capture() RPC call */
+ MISC_FUNC_SET_ARI = 3, /* Index for misc_set_ari() RPC call */
+ MISC_FUNC_BOOT_STATUS = 7, /* Index for misc_boot_status() RPC call */
} misc_func_t;
/* Functions */
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
sc_err_t sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource,
if (val != NULL)
*val = RPC_D32(&msg, 0);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
-sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_rsrc_t resource_mst, uint16_t ari, bool enable)
+sc_err_t sc_misc_set_max_dma_group(sc_ipc_t ipc, sc_rm_pt_t pt,
+ sc_misc_dma_group_t max)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_SET_ARI;
- RPC_D16(&msg, 0) = resource;
- RPC_D16(&msg, 2) = resource_mst;
- RPC_D16(&msg, 4) = ari;
- RPC_D8(&msg, 6) = enable;
- RPC_SIZE(&msg) = 3;
+ RPC_FUNC(&msg) = MISC_FUNC_SET_MAX_DMA_GROUP;
+ RPC_D8(&msg, 0) = pt;
+ RPC_D8(&msg, 1) = max;
+ RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
-sc_err_t sc_misc_set_max_dma_group(sc_ipc_t ipc, sc_rm_pt_t pt,
- sc_misc_dma_group_t max)
+sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_misc_dma_group_t group)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_SET_MAX_DMA_GROUP;
- RPC_D8(&msg, 0) = pt;
- RPC_D8(&msg, 1) = max;
+ RPC_FUNC(&msg) = MISC_FUNC_SET_DMA_GROUP;
+ RPC_D16(&msg, 0) = resource;
+ RPC_D8(&msg, 2) = group;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
-sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_misc_dma_group_t group)
+sc_err_t sc_misc_seco_image_load(sc_ipc_t ipc, uint32_t addr_src,
+ uint32_t addr_dst, uint32_t len, bool fw)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_SET_DMA_GROUP;
- RPC_D16(&msg, 0) = resource;
- RPC_D8(&msg, 2) = group;
- RPC_SIZE(&msg) = 2;
+ RPC_FUNC(&msg) = MISC_FUNC_SECO_IMAGE_LOAD;
+ RPC_D32(&msg, 0) = addr_src;
+ RPC_D32(&msg, 4) = addr_dst;
+ RPC_D32(&msg, 8) = len;
+ RPC_D8(&msg, 12) = fw;
+ RPC_SIZE(&msg) = 5;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
-sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, bool enable)
+sc_err_t sc_misc_seco_authenticate(sc_ipc_t ipc,
+ sc_misc_seco_auth_cmd_t cmd,
+ uint32_t addr_meta)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_WAVEFORM_CAPTURE;
- RPC_D8(&msg, 0) = enable;
- RPC_SIZE(&msg) = 2;
+ RPC_FUNC(&msg) = MISC_FUNC_SECO_AUTHENTICATE;
+ RPC_D32(&msg, 0) = addr_meta;
+ RPC_D8(&msg, 4) = cmd;
+ RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
-void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status)
+void sc_misc_debug_out(sc_ipc_t ipc, uint8_t ch)
{
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_BOOT_STATUS;
- RPC_D8(&msg, 0) = status;
+ RPC_FUNC(&msg) = MISC_FUNC_DEBUG_OUT;
+ RPC_D8(&msg, 0) = ch;
RPC_SIZE(&msg) = 2;
- sc_call_rpc(ipc, &msg, true);
+ sc_call_rpc(ipc, &msg, false);
+
+ return;
}
-sc_err_t sc_misc_seco_image_load(sc_ipc_t ipc, uint32_t addr_src,
- uint32_t addr_dst, uint32_t len, bool fw)
+sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, bool enable)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_SECO_IMAGE_LOAD;
- RPC_D32(&msg, 0) = addr_src;
- RPC_D32(&msg, 4) = addr_dst;
- RPC_D32(&msg, 8) = len;
- RPC_D8(&msg, 12) = fw;
- RPC_SIZE(&msg) = 5;
+ RPC_FUNC(&msg) = MISC_FUNC_WAVEFORM_CAPTURE;
+ RPC_D8(&msg, 0) = enable;
+ RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
-sc_err_t sc_misc_seco_authenticate(sc_ipc_t ipc,
- sc_misc_seco_auth_cmd_t cmd,
- uint32_t addr_meta)
+sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_rsrc_t resource_mst, uint16_t ari, bool enable)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_MISC;
- RPC_FUNC(&msg) = MISC_FUNC_SECO_AUTHENTICATE;
- RPC_D32(&msg, 0) = addr_meta;
- RPC_D8(&msg, 4) = cmd;
+ RPC_FUNC(&msg) = MISC_FUNC_SET_ARI;
+ RPC_D16(&msg, 0) = resource;
+ RPC_D16(&msg, 2) = resource_mst;
+ RPC_D16(&msg, 4) = ari;
+ RPC_D8(&msg, 6) = enable;
RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
+}
+
+void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status)
+{
+ sc_rpc_msg_t msg;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = SC_RPC_SVC_MISC;
+ RPC_FUNC(&msg) = MISC_FUNC_BOOT_STATUS;
+ RPC_D8(&msg, 0) = status;
+ RPC_SIZE(&msg) = 2;
+
+ sc_call_rpc(ipc, &msg, true);
+
+ return;
}
/**@}*/
* This type is used to indicate RPC PAD function calls.
*/
typedef enum pad_func_e {
- PAD_FUNC_UNKNOWN, /* Unknown function */
- PAD_FUNC_SET_MUX, /* Index for pad_set_mux() RPC call */
- PAD_FUNC_SET_GP, /* Index for pad_set_gp() RPC call */
- PAD_FUNC_SET_GP_28LPP, /* Index for pad_set_gp_28lpp() RPC call */
- PAD_FUNC_SET_WAKEUP, /* Index for pad_set_wakeup() RPC call */
- PAD_FUNC_SET_ALL, /* Index for pad_set_all() RPC call */
- PAD_FUNC_GET_MUX, /* Index for pad_get_mux() RPC call */
- PAD_FUNC_GET_GP, /* Index for pad_get_gp() RPC call */
- PAD_FUNC_GET_GP_28LPP, /* Index for pad_get_gp_28lpp() RPC call */
- PAD_FUNC_GET_WAKEUP, /* Index for pad_get_wakeup() RPC call */
- PAD_FUNC_GET_ALL, /* Index for pad_get_all() RPC call */
- PAD_FUNC_SET_GP_28FDSOI, /* Index for pad_set_gp_28fdsoi() RPC call */
- PAD_FUNC_GET_GP_28FDSOI, /* Index for pad_get_gp_28fdsoi() RPC call */
- PAD_FUNC_SET_GP_28FDSOI_COMP, /* Index for pad_set_gp_28fdsoi_comp() RPC call */
- PAD_FUNC_GET_GP_28FDSOI_COMP, /* Index for pad_get_gp_28fdsoi_comp() RPC call */
- PAD_FUNC_SET, /* Index for pad_set() RPC call */
- PAD_FUNC_GET, /* Index for pad_get() RPC call */
+ PAD_FUNC_UNKNOWN = 0, /* Unknown function */
+ PAD_FUNC_SET_MUX = 1, /* Index for pad_set_mux() RPC call */
+ PAD_FUNC_GET_MUX = 6, /* Index for pad_get_mux() RPC call */
+ PAD_FUNC_SET_GP = 2, /* Index for pad_set_gp() RPC call */
+ PAD_FUNC_GET_GP = 7, /* Index for pad_get_gp() RPC call */
+ PAD_FUNC_SET_WAKEUP = 4, /* Index for pad_set_wakeup() RPC call */
+ PAD_FUNC_GET_WAKEUP = 9, /* Index for pad_get_wakeup() RPC call */
+ PAD_FUNC_SET_ALL = 5, /* Index for pad_set_all() RPC call */
+ PAD_FUNC_GET_ALL = 10, /* Index for pad_get_all() RPC call */
+ PAD_FUNC_SET = 15, /* Index for pad_set() RPC call */
+ PAD_FUNC_GET = 16, /* Index for pad_get() RPC call */
+ PAD_FUNC_SET_GP_28LPP = 3, /* Index for pad_set_gp_28lpp() RPC call */
+ PAD_FUNC_GET_GP_28LPP = 8, /* Index for pad_get_gp_28lpp() RPC call */
+ PAD_FUNC_SET_GP_28FDSOI = 11, /* Index for pad_set_gp_28fdsoi() RPC call */
+ PAD_FUNC_GET_GP_28FDSOI = 12, /* Index for pad_get_gp_28fdsoi() RPC call */
+ PAD_FUNC_SET_GP_28FDSOI_COMP = 13, /* Index for pad_set_gp_28fdsoi_comp() RPC call */
+ PAD_FUNC_GET_GP_28FDSOI_COMP = 14, /* Index for pad_get_gp_28fdsoi_comp() RPC call */
} pad_func_t;
/* Functions */
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
+}
+
+sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pin_t pin,
+ uint8_t *mux, sc_pad_config_t *config,
+ sc_pad_iso_t *iso)
+{
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = PAD_FUNC_GET_MUX;
+ RPC_D16(&msg, 0) = pin;
+ RPC_SIZE(&msg) = 2;
+
+ sc_call_rpc(ipc, &msg, false);
+
+ result = RPC_R8(&msg);
+ if (mux != NULL)
+ *mux = RPC_D8(&msg, 0);
+ if (config != NULL)
+ *config = RPC_D8(&msg, 1);
+ if (iso != NULL)
+ *iso = RPC_D8(&msg, 2);
+ return (sc_err_t)result;
}
sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pin_t pin, uint32_t ctrl)
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
-sc_err_t sc_pad_set_gp_28lpp(sc_ipc_t ipc, sc_pin_t pin,
- sc_pad_28lpp_dse_t dse, bool sre, bool hys,
- bool pe, sc_pad_28lpp_ps_t ps)
+sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pin_t pin, uint32_t *ctrl)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_SET_GP_28LPP;
+ RPC_FUNC(&msg) = PAD_FUNC_GET_GP;
RPC_D16(&msg, 0) = pin;
- RPC_D8(&msg, 2) = dse;
- RPC_D8(&msg, 3) = ps;
- RPC_D8(&msg, 4) = sre;
- RPC_D8(&msg, 5) = hys;
- RPC_D8(&msg, 6) = pe;
- RPC_SIZE(&msg) = 3;
+ RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
+ if (ctrl != NULL)
+ *ctrl = RPC_D32(&msg, 0);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pin_t pin, sc_pad_wakeup_t wakeup)
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
+}
+
+sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pin_t pin, sc_pad_wakeup_t *wakeup)
+{
+ sc_rpc_msg_t msg;
+ uint8_t result;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+ RPC_FUNC(&msg) = PAD_FUNC_GET_WAKEUP;
+ RPC_D16(&msg, 0) = pin;
+ RPC_SIZE(&msg) = 2;
+
+ sc_call_rpc(ipc, &msg, false);
+
+ result = RPC_R8(&msg);
+ if (wakeup != NULL)
+ *wakeup = RPC_D8(&msg, 0);
+ return (sc_err_t)result;
}
sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pin_t pin, uint8_t mux,
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
-sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pin_t pin,
- uint8_t *mux, sc_pad_config_t *config,
- sc_pad_iso_t *iso)
+sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pin_t pin, uint8_t *mux,
+ sc_pad_config_t *config, sc_pad_iso_t *iso,
+ uint32_t *ctrl, sc_pad_wakeup_t *wakeup)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET_MUX;
+ RPC_FUNC(&msg) = PAD_FUNC_GET_ALL;
RPC_D16(&msg, 0) = pin;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
+ if (ctrl != NULL)
+ *ctrl = RPC_D32(&msg, 0);
result = RPC_R8(&msg);
if (mux != NULL)
- *mux = RPC_D8(&msg, 0);
+ *mux = RPC_D8(&msg, 4);
if (config != NULL)
- *config = RPC_D8(&msg, 1);
+ *config = RPC_D8(&msg, 5);
if (iso != NULL)
- *iso = RPC_D8(&msg, 2);
- return (sc_err_t) result;
+ *iso = RPC_D8(&msg, 6);
+ if (wakeup != NULL)
+ *wakeup = RPC_D8(&msg, 7);
+ return (sc_err_t)result;
}
-sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pin_t pin, uint32_t *ctrl)
+sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pin_t pin, uint32_t val)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET_GP;
- RPC_D16(&msg, 0) = pin;
- RPC_SIZE(&msg) = 2;
+ RPC_FUNC(&msg) = PAD_FUNC_SET;
+ RPC_D32(&msg, 0) = val;
+ RPC_D16(&msg, 4) = pin;
+ RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
- if (ctrl != NULL)
- *ctrl = RPC_D32(&msg, 0);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
-sc_err_t sc_pad_get_gp_28lpp(sc_ipc_t ipc, sc_pin_t pin,
- sc_pad_28lpp_dse_t *dse, bool *sre, bool *hys,
- bool *pe, sc_pad_28lpp_ps_t *ps)
+sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pin_t pin, uint32_t *val)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET_GP_28LPP;
+ RPC_FUNC(&msg) = PAD_FUNC_GET;
RPC_D16(&msg, 0) = pin;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
+ if (val != NULL)
+ *val = RPC_D32(&msg, 0);
result = RPC_R8(&msg);
- if (dse != NULL)
- *dse = RPC_D8(&msg, 0);
- if (ps != NULL)
- *ps = RPC_D8(&msg, 1);
- if (sre != NULL)
- *sre = RPC_D8(&msg, 2);
- if (hys != NULL)
- *hys = RPC_D8(&msg, 3);
- if (pe != NULL)
- *pe = RPC_D8(&msg, 4);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
-sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pin_t pin, sc_pad_wakeup_t *wakeup)
+sc_err_t sc_pad_set_gp_28lpp(sc_ipc_t ipc, sc_pin_t pin,
+ sc_pad_28lpp_dse_t dse, bool sre, bool hys,
+ bool pe, sc_pad_28lpp_ps_t ps)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET_WAKEUP;
+ RPC_FUNC(&msg) = PAD_FUNC_SET_GP_28LPP;
RPC_D16(&msg, 0) = pin;
- RPC_SIZE(&msg) = 2;
+ RPC_D8(&msg, 2) = dse;
+ RPC_D8(&msg, 3) = ps;
+ RPC_D8(&msg, 4) = sre;
+ RPC_D8(&msg, 5) = hys;
+ RPC_D8(&msg, 6) = pe;
+ RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- if (wakeup != NULL)
- *wakeup = RPC_D8(&msg, 0);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
-sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pin_t pin, uint8_t *mux,
- sc_pad_config_t *config, sc_pad_iso_t *iso,
- uint32_t *ctrl, sc_pad_wakeup_t *wakeup)
+sc_err_t sc_pad_get_gp_28lpp(sc_ipc_t ipc, sc_pin_t pin,
+ sc_pad_28lpp_dse_t *dse, bool *sre, bool *hys,
+ bool *pe, sc_pad_28lpp_ps_t *ps)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET_ALL;
+ RPC_FUNC(&msg) = PAD_FUNC_GET_GP_28LPP;
RPC_D16(&msg, 0) = pin;
RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
- if (ctrl != NULL)
- *ctrl = RPC_D32(&msg, 0);
result = RPC_R8(&msg);
- if (mux != NULL)
- *mux = RPC_D8(&msg, 4);
- if (config != NULL)
- *config = RPC_D8(&msg, 5);
- if (iso != NULL)
- *iso = RPC_D8(&msg, 6);
- if (wakeup != NULL)
- *wakeup = RPC_D8(&msg, 7);
- return (sc_err_t) result;
+ if (dse != NULL)
+ *dse = RPC_D8(&msg, 0);
+ if (ps != NULL)
+ *ps = RPC_D8(&msg, 1);
+ if (sre != NULL)
+ *sre = RPC_D8(&msg, 2);
+ if (hys != NULL)
+ *hys = RPC_D8(&msg, 3);
+ if (pe != NULL)
+ *pe = RPC_D8(&msg, 4);
+ return (sc_err_t)result;
}
sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pin_t pin,
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pin_t pin,
*dse = RPC_D8(&msg, 0);
if (ps != NULL)
*ps = RPC_D8(&msg, 1);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pin_t pin,
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pin_t pin,
*nasrc_sel = RPC_D8(&msg, 5);
if (compok != NULL)
*compok = RPC_D8(&msg, 6);
- return (sc_err_t) result;
-}
-
-sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pin_t pin, uint32_t val)
-{
- sc_rpc_msg_t msg;
- uint8_t result;
-
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_SET;
- RPC_D32(&msg, 0) = val;
- RPC_D16(&msg, 4) = pin;
- RPC_SIZE(&msg) = 3;
-
- sc_call_rpc(ipc, &msg, false);
-
- result = RPC_R8(&msg);
- return (sc_err_t) result;
-}
-
-sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pin_t pin, uint32_t *val)
-{
- sc_rpc_msg_t msg;
- uint8_t result;
-
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PAD;
- RPC_FUNC(&msg) = PAD_FUNC_GET;
- RPC_D16(&msg, 0) = pin;
- RPC_SIZE(&msg) = 2;
-
- sc_call_rpc(ipc, &msg, false);
-
- if (val != NULL)
- *val = RPC_D32(&msg, 0);
- result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
/**@}*/
* This type is used to indicate RPC PM function calls.
*/
typedef enum pm_func_e {
- PM_FUNC_UNKNOWN, /* Unknown function */
- PM_FUNC_SET_SYS_POWER_MODE, /* Index for pm_set_sys_power_mode() RPC call */
- PM_FUNC_GET_SYS_POWER_MODE, /* Index for pm_get_sys_power_mode() RPC call */
- PM_FUNC_SET_RESOURCE_POWER_MODE, /* Index for pm_set_resource_power_mode() RPC call */
- PM_FUNC_GET_RESOURCE_POWER_MODE, /* Index for pm_get_resource_power_mode() RPC call */
- PM_FUNC_SET_CLOCK_RATE, /* Index for pm_set_clock_rate() RPC call */
- PM_FUNC_GET_CLOCK_RATE, /* Index for pm_get_clock_rate() RPC call */
- PM_FUNC_CLOCK_ENABLE, /* Index for pm_clock_enable() RPC call */
- PM_FUNC_BOOT, /* Index for pm_boot() RPC call */
- PM_FUNC_REBOOT, /* Index for pm_reboot() RPC call */
- PM_FUNC_RESET_REASON, /* Index for pm_reset_reason() RPC call */
- PM_FUNC_CPU_START, /* Index for pm_cpu_start() RPC call */
- PM_FUNC_REBOOT_PARTITION, /* Index for pm_reboot_partition() RPC call */
- PM_FUNC_RESET, /* Index for pm_reset() RPC call */
+ PM_FUNC_UNKNOWN = 0, /* Unknown function */
+ PM_FUNC_SET_SYS_POWER_MODE = 1, /* Index for pm_set_sys_power_mode() RPC call */
+ PM_FUNC_GET_SYS_POWER_MODE = 2, /* Index for pm_get_sys_power_mode() RPC call */
+ PM_FUNC_SET_RESOURCE_POWER_MODE = 3, /* Index for pm_set_resource_power_mode() RPC call */
+ PM_FUNC_GET_RESOURCE_POWER_MODE = 4, /* Index for pm_get_resource_power_mode() RPC call */
+ PM_FUNC_SET_CLOCK_RATE = 5, /* Index for pm_set_clock_rate() RPC call */
+ PM_FUNC_GET_CLOCK_RATE = 6, /* Index for pm_get_clock_rate() RPC call */
+ PM_FUNC_CLOCK_ENABLE = 7, /* Index for pm_clock_enable() RPC call */
+ PM_FUNC_RESET = 13, /* Index for pm_reset() RPC call */
+ PM_FUNC_RESET_REASON = 10, /* Index for pm_reset_reason() RPC call */
+ PM_FUNC_BOOT = 8, /* Index for pm_boot() RPC call */
+ PM_FUNC_REBOOT = 9, /* Index for pm_reboot() RPC call */
+ PM_FUNC_REBOOT_PARTITION = 12, /* Index for pm_reboot_partition() RPC call */
+ PM_FUNC_CPU_START = 11, /* Index for pm_cpu_start() RPC call */
} pm_func_t;
/* Functions */
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
result = RPC_R8(&msg);
if (mode != NULL)
*mode = RPC_D8(&msg, 0);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
result = RPC_R8(&msg);
if (mode != NULL)
*mode = RPC_D8(&msg, 0);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
*rate = RPC_D32(&msg, 0);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
if (rate != NULL)
*rate = RPC_D32(&msg, 0);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource,
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
-sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt,
- sc_rsrc_t resource_cpu, sc_faddr_t boot_addr,
- sc_rsrc_t resource_mu, sc_rsrc_t resource_dev)
+sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_BOOT;
- RPC_D32(&msg, 0) = boot_addr >> 32;
- RPC_D32(&msg, 4) = boot_addr;
- RPC_D16(&msg, 8) = resource_cpu;
- RPC_D16(&msg, 10) = resource_mu;
- RPC_D16(&msg, 12) = resource_dev;
- RPC_D8(&msg, 14) = pt;
- RPC_SIZE(&msg) = 5;
+ RPC_FUNC(&msg) = PM_FUNC_RESET;
+ RPC_D8(&msg, 0) = type;
+ RPC_SIZE(&msg) = 2;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
-}
-
-void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type)
-{
- sc_rpc_msg_t msg;
-
- RPC_VER(&msg) = SC_RPC_VERSION;
- RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_REBOOT;
- RPC_D8(&msg, 0) = type;
- RPC_SIZE(&msg) = 2;
-
- sc_call_rpc(ipc, &msg, true);
+ return (sc_err_t)result;
}
sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason)
result = RPC_R8(&msg);
if (reason != NULL)
*reason = RPC_D8(&msg, 0);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
-sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, bool enable,
- sc_faddr_t address)
+sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt,
+ sc_rsrc_t resource_cpu, sc_faddr_t boot_addr,
+ sc_rsrc_t resource_mu, sc_rsrc_t resource_dev)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_CPU_START;
- RPC_D32(&msg, 0) = address >> 32;
- RPC_D32(&msg, 4) = address;
- RPC_D16(&msg, 8) = resource;
- RPC_D8(&msg, 10) = enable;
- RPC_SIZE(&msg) = 4;
+ RPC_FUNC(&msg) = PM_FUNC_BOOT;
+ RPC_D32(&msg, 0) = boot_addr >> 32;
+ RPC_D32(&msg, 4) = boot_addr;
+ RPC_D16(&msg, 8) = resource_cpu;
+ RPC_D16(&msg, 10) = resource_mu;
+ RPC_D16(&msg, 12) = resource_dev;
+ RPC_D8(&msg, 14) = pt;
+ RPC_SIZE(&msg) = 5;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
+}
+
+void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type)
+{
+ sc_rpc_msg_t msg;
+
+ RPC_VER(&msg) = SC_RPC_VERSION;
+ RPC_SVC(&msg) = SC_RPC_SVC_PM;
+ RPC_FUNC(&msg) = PM_FUNC_REBOOT;
+ RPC_D8(&msg, 0) = type;
+ RPC_SIZE(&msg) = 2;
+
+ sc_call_rpc(ipc, &msg, true);
+
+ return;
}
sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt,
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
-sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type)
+sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, bool enable,
+ sc_faddr_t address)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_PM;
- RPC_FUNC(&msg) = PM_FUNC_RESET;
- RPC_D8(&msg, 0) = type;
- RPC_SIZE(&msg) = 2;
+ RPC_FUNC(&msg) = PM_FUNC_CPU_START;
+ RPC_D32(&msg, 0) = address >> 32;
+ RPC_D32(&msg, 4) = address;
+ RPC_D16(&msg, 8) = resource;
+ RPC_D8(&msg, 10) = enable;
+ RPC_SIZE(&msg) = 4;
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
/**@}*/
* This type is used to indicate RPC RM function calls.
*/
typedef enum rm_func_e {
- RM_FUNC_UNKNOWN, /* Unknown function */
- RM_FUNC_PARTITION_ALLOC, /* Index for rm_partition_alloc() RPC call */
- RM_FUNC_PARTITION_FREE, /* Index for rm_partition_free() RPC call */
- RM_FUNC_PARTITION_STATIC, /* Index for rm_partition_static() RPC call */
- RM_FUNC_PARTITION_LOCK, /* Index for rm_partition_lock() RPC call */
- RM_FUNC_GET_PARTITION, /* Index for rm_get_partition() RPC call */
- RM_FUNC_SET_PARENT, /* Index for rm_set_parent() RPC call */
- RM_FUNC_MOVE_ALL, /* Index for rm_move_all() RPC call */
- RM_FUNC_ASSIGN_RESOURCE, /* Index for rm_assign_resource() RPC call */
- RM_FUNC_SET_RESOURCE_MOVABLE, /* Index for rm_set_resource_movable() RPC call */
- RM_FUNC_SET_MASTER_ATTRIBUTES, /* Index for rm_set_master_attributes() RPC call */
- RM_FUNC_SET_MASTER_SID, /* Index for rm_set_master_sid() RPC call */
- RM_FUNC_SET_PERIPHERAL_PERMISSIONS, /* Index for rm_set_peripheral_permissions() RPC call */
- RM_FUNC_IS_RESOURCE_OWNED, /* Index for rm_is_resource_owned() RPC call */
- RM_FUNC_IS_RESOURCE_MASTER, /* Index for rm_is_resource_master() RPC call */
- RM_FUNC_IS_RESOURCE_PERIPHERAL, /* Index for rm_is_resource_peripheral() RPC call */
- RM_FUNC_GET_RESOURCE_INFO, /* Index for rm_get_resource_info() RPC call */
- RM_FUNC_MEMREG_ALLOC, /* Index for rm_memreg_alloc() RPC call */
- RM_FUNC_MEMREG_FREE, /* Index for rm_memreg_free() RPC call */
- RM_FUNC_ASSIGN_MEMREG, /* Index for rm_assign_memreg() RPC call */
- RM_FUNC_SET_MEMREG_PERMISSIONS, /* Index for rm_set_memreg_permissions() RPC call */
- RM_FUNC_IS_MEMREG_OWNED, /* Index for rm_is_memreg_owned() RPC call */
- RM_FUNC_GET_MEMREG_INFO, /* Index for rm_get_memreg_info() RPC call */
- RM_FUNC_ASSIGN_PIN, /* Index for rm_assign_pin() RPC call */
- RM_FUNC_SET_PIN_MOVABLE, /* Index for rm_set_pin_movable() RPC call */
- RM_FUNC_IS_PIN_OWNED, /* Index for rm_is_pin_owned() RPC call */
- RM_FUNC_GET_DID, /* Index for rm_get_did() RPC call */
+ RM_FUNC_UNKNOWN = 0, /* Unknown function */
+ RM_FUNC_PARTITION_ALLOC = 1, /* Index for rm_partition_alloc() RPC call */
+ RM_FUNC_PARTITION_FREE = 2, /* Index for rm_partition_free() RPC call */
+ RM_FUNC_GET_DID = 26, /* Index for rm_get_did() RPC call */
+ RM_FUNC_PARTITION_STATIC = 3, /* Index for rm_partition_static() RPC call */
+ RM_FUNC_PARTITION_LOCK = 4, /* Index for rm_partition_lock() RPC call */
+ RM_FUNC_GET_PARTITION = 5, /* Index for rm_get_partition() RPC call */
+ RM_FUNC_SET_PARENT = 6, /* Index for rm_set_parent() RPC call */
+ RM_FUNC_MOVE_ALL = 7, /* Index for rm_move_all() RPC call */
+ RM_FUNC_ASSIGN_RESOURCE = 8, /* Index for rm_assign_resource() RPC call */
+ RM_FUNC_SET_RESOURCE_MOVABLE = 9, /* Index for rm_set_resource_movable() RPC call */
+ RM_FUNC_SET_MASTER_ATTRIBUTES = 10, /* Index for rm_set_master_attributes() RPC call */
+ RM_FUNC_SET_MASTER_SID = 11, /* Index for rm_set_master_sid() RPC call */
+ RM_FUNC_SET_PERIPHERAL_PERMISSIONS = 12, /* Index for rm_set_peripheral_permissions() RPC call */
+ RM_FUNC_IS_RESOURCE_OWNED = 13, /* Index for rm_is_resource_owned() RPC call */
+ RM_FUNC_IS_RESOURCE_MASTER = 14, /* Index for rm_is_resource_master() RPC call */
+ RM_FUNC_IS_RESOURCE_PERIPHERAL = 15, /* Index for rm_is_resource_peripheral() RPC call */
+ RM_FUNC_GET_RESOURCE_INFO = 16, /* Index for rm_get_resource_info() RPC call */
+ RM_FUNC_MEMREG_ALLOC = 17, /* Index for rm_memreg_alloc() RPC call */
+ RM_FUNC_MEMREG_FREE = 18, /* Index for rm_memreg_free() RPC call */
+ RM_FUNC_ASSIGN_MEMREG = 19, /* Index for rm_assign_memreg() RPC call */
+ RM_FUNC_SET_MEMREG_PERMISSIONS = 20, /* Index for rm_set_memreg_permissions() RPC call */
+ RM_FUNC_IS_MEMREG_OWNED = 21, /* Index for rm_is_memreg_owned() RPC call */
+ RM_FUNC_GET_MEMREG_INFO = 22, /* Index for rm_get_memreg_info() RPC call */
+ RM_FUNC_ASSIGN_PIN = 23, /* Index for rm_assign_pin() RPC call */
+ RM_FUNC_SET_PIN_MOVABLE = 24, /* Index for rm_set_pin_movable() RPC call */
+ RM_FUNC_IS_PIN_OWNED = 25, /* Index for rm_is_pin_owned() RPC call */
} rm_func_t;
/* Functions */
* This type is used to indicate RPC TIMER function calls.
*/
typedef enum timer_func_e {
- TIMER_FUNC_UNKNOWN, /* Unknown function */
- TIMER_FUNC_SET_WDOG_TIMEOUT, /* Index for timer_set_wdog_timeout() RPC call */
- TIMER_FUNC_START_WDOG, /* Index for timer_start_wdog() RPC call */
- TIMER_FUNC_STOP_WDOG, /* Index for timer_stop_wdog() RPC call */
- TIMER_FUNC_PING_WDOG, /* Index for timer_ping_wdog() RPC call */
- TIMER_FUNC_GET_WDOG_STATUS, /* Index for timer_get_wdog_status() RPC call */
- TIMER_FUNC_SET_RTC_TIME, /* Index for timer_set_rtc_time() RPC call */
- TIMER_FUNC_GET_RTC_TIME, /* Index for timer_get_rtc_time() RPC call */
- TIMER_FUNC_SET_RTC_ALARM, /* Index for timer_set_rtc_alarm() RPC call */
- TIMER_FUNC_GET_RTC_SEC1970, /* Index for timer_get_rtc_sec1970() RPC call */
+ TIMER_FUNC_UNKNOWN = 0, /* Unknown function */
+ TIMER_FUNC_SET_WDOG_TIMEOUT = 1, /* Index for timer_set_wdog_timeout() RPC call */
+ TIMER_FUNC_START_WDOG = 2, /* Index for timer_start_wdog() RPC call */
+ TIMER_FUNC_STOP_WDOG = 3, /* Index for timer_stop_wdog() RPC call */
+ TIMER_FUNC_PING_WDOG = 4, /* Index for timer_ping_wdog() RPC call */
+ TIMER_FUNC_GET_WDOG_STATUS = 5, /* Index for timer_get_wdog_status() RPC call */
+ TIMER_FUNC_SET_RTC_TIME = 6, /* Index for timer_set_rtc_time() RPC call */
+ TIMER_FUNC_GET_RTC_TIME = 7, /* Index for timer_get_rtc_time() RPC call */
+ TIMER_FUNC_GET_RTC_SEC1970 = 9, /* Index for timer_get_rtc_sec1970() RPC call */
+ TIMER_FUNC_SET_RTC_ALARM = 8, /* Index for timer_set_rtc_alarm() RPC call */
} timer_func_t;
/* Functions */
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, bool lock)
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
sc_err_t sc_timer_stop_wdog(sc_ipc_t ipc)
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
sc_err_t sc_timer_ping_wdog(sc_ipc_t ipc)
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc,
if (remaining_time != NULL)
*remaining_time = RPC_D32(&msg, 8);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon,
sc_call_rpc(ipc, &msg, false);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
sc_err_t sc_timer_get_rtc_time(sc_ipc_t ipc, uint16_t *year, uint8_t *mon,
*min = RPC_D8(&msg, 5);
if (sec != NULL)
*sec = RPC_D8(&msg, 6);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
-sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon,
- uint8_t day, uint8_t hour, uint8_t min,
- uint8_t sec)
+sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_SET_RTC_ALARM;
- RPC_D16(&msg, 0) = year;
- RPC_D8(&msg, 2) = mon;
- RPC_D8(&msg, 3) = day;
- RPC_D8(&msg, 4) = hour;
- RPC_D8(&msg, 5) = min;
- RPC_D8(&msg, 6) = sec;
- RPC_SIZE(&msg) = 3;
+ RPC_FUNC(&msg) = TIMER_FUNC_GET_RTC_SEC1970;
+ RPC_SIZE(&msg) = 1;
sc_call_rpc(ipc, &msg, false);
+ if (sec != NULL)
+ *sec = RPC_D32(&msg, 0);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
-sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec)
+sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon,
+ uint8_t day, uint8_t hour, uint8_t min,
+ uint8_t sec)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = SC_RPC_SVC_TIMER;
- RPC_FUNC(&msg) = TIMER_FUNC_GET_RTC_SEC1970;
- RPC_SIZE(&msg) = 1;
+ RPC_FUNC(&msg) = TIMER_FUNC_SET_RTC_ALARM;
+ RPC_D16(&msg, 0) = year;
+ RPC_D8(&msg, 2) = mon;
+ RPC_D8(&msg, 3) = day;
+ RPC_D8(&msg, 4) = hour;
+ RPC_D8(&msg, 5) = min;
+ RPC_D8(&msg, 6) = sec;
+ RPC_SIZE(&msg) = 3;
sc_call_rpc(ipc, &msg, false);
- if (sec != NULL)
- *sec = RPC_D32(&msg, 0);
result = RPC_R8(&msg);
- return (sc_err_t) result;
+ return (sc_err_t)result;
}
/**@}*/
* SPDX-License-Identifier: GPL-2.0+
*/
-/*==========================================================================*/
/*!
- * @file
- *
* Header file used to configure SoC pin list.
*/
-/*==========================================================================*/
-
-/* DO NOT EDIT - This file auto generated by bin/pins_h.pl */
#ifndef _SC_PINS_H
#define _SC_PINS_H
/* Defines */
-#define SC_P_ALL UINT16_MAX //!< All pins
+#define SC_P_ALL UINT16_MAX /* All pins */
/*!
* @name Pin Definitions
*/
/*@{*/
-#define SC_P_PCIE_CTRL0_CLKREQ_B 0 //!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO0.IO04
-#define SC_P_PCIE_CTRL0_WAKE_B 1 //!< HSIO.PCIE0.WAKE_B, LSIO.GPIO0.IO05
-#define SC_P_PCIE_CTRL0_PERST_B 2 //!< HSIO.PCIE0.PERST_B, LSIO.GPIO0.IO06
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 //!<
-#define SC_P_USB_SS3_TC0 4 //!< ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO0.IO00
-#define SC_P_USB_SS3_TC1 5 //!< ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO0.IO01
-#define SC_P_USB_SS3_TC2 6 //!< ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO0.IO02
-#define SC_P_USB_SS3_TC3 7 //!< ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO0.IO03
-#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 //!<
-#define SC_P_EMMC0_CLK 9 //!< CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.KPP0.COL0, LSIO.GPIO0.IO17
-#define SC_P_EMMC0_CMD 10 //!< CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.KPP0.COL1, LSIO.GPIO0.IO18
-#define SC_P_EMMC0_DATA0 11 //!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.KPP0.COL2, LSIO.GPIO0.IO19
-#define SC_P_EMMC0_DATA1 12 //!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.KPP0.COL3, LSIO.GPIO0.IO20
-#define SC_P_EMMC0_DATA2 13 //!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.KPP0.COL4, LSIO.GPIO0.IO21
-#define SC_P_EMMC0_DATA3 14 //!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.KPP0.COL5, LSIO.GPIO0.IO22
-#define SC_P_EMMC0_DATA4 15 //!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.KPP0.ROW0, CONN.EMMC0.WP
-#define SC_P_EMMC0_DATA5 16 //!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.KPP0.ROW1, CONN.EMMC0.VSELECT
-#define SC_P_EMMC0_DATA6 17 //!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.KPP0.ROW2, CONN.MLB.CLK
-#define SC_P_EMMC0_DATA7 18 //!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.KPP0.ROW3, CONN.MLB.SIG
-#define SC_P_EMMC0_STROBE 19 //!< CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.KPP0.ROW4, CONN.MLB.DATA
-#define SC_P_EMMC0_RESET_B 20 //!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.KPP0.ROW5, LSIO.GPIO0.IO28
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 21 //!<
-#define SC_P_USDHC1_RESET_B 22 //!< CONN.USDHC1.RESET_B, CONN.NAND.RE_N, CONN.MLB.SIG, LSIO.GPIO0.IO07
-#define SC_P_USDHC1_VSELECT 23 //!< CONN.USDHC1.VSELECT, CONN.NAND.RE_P, CONN.MLB.CLK, LSIO.GPIO0.IO08
-#define SC_P_USDHC1_WP 24 //!< CONN.USDHC1.WP, CONN.NAND.DQS_N, LSIO.GPIO0.IO09
-#define SC_P_USDHC1_CD_B 25 //!< CONN.USDHC1.CD_B, CONN.NAND.DQS_P, CONN.MLB.DATA, LSIO.GPIO0.IO10
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 26 //!<
-#define SC_P_USDHC1_CLK 27 //!< CONN.USDHC1.CLK, ADMA.MQS.R, LSIO.GPIO0.IO11
-#define SC_P_USDHC1_CMD 28 //!< CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.L, LSIO.GPIO0.IO12
-#define SC_P_USDHC1_DATA0 29 //!< CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.UART4.RX, LSIO.GPIO0.IO13
-#define SC_P_USDHC1_DATA1 30 //!< CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART4.TX, LSIO.GPIO0.IO14
-#define SC_P_USDHC1_DATA2 31 //!< CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART4.CTS_B, LSIO.GPIO0.IO15
-#define SC_P_USDHC1_DATA3 32 //!< CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART4.RTS_B, LSIO.GPIO0.IO16
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 33 //!<
-#define SC_P_ENET0_RGMII_TXC 34 //!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B
-#define SC_P_ENET0_RGMII_TX_CTL 35 //!< CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B
-#define SC_P_ENET0_RGMII_TXD0 36 //!< CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT
-#define SC_P_ENET0_RGMII_TXD1 37 //!< CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP
-#define SC_P_ENET0_RGMII_TXD2 38 //!< CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, LSIO.GPIO1.IO05
-#define SC_P_ENET0_RGMII_TXD3 39 //!< CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, CONN.USDHC1.CD_B
-#define SC_P_ENET0_RGMII_RXC 40 //!< CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK
-#define SC_P_ENET0_RGMII_RX_CTL 41 //!< CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD
-#define SC_P_ENET0_RGMII_RXD0 42 //!< CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0
-#define SC_P_ENET0_RGMII_RXD1 43 //!< CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1
-#define SC_P_ENET0_RGMII_RXD2 44 //!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2
-#define SC_P_ENET0_RGMII_RXD3 45 //!< CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 46 //!<
-#define SC_P_ENET0_REFCLK_125M_25M 47 //!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO1.IO00
-#define SC_P_ENET0_MDIO 48 //!< CONN.ENET0.MDIO, ADMA.I2C4.SDA, CONN.ENET1.MDIO, LSIO.GPIO0.IO29
-#define SC_P_ENET0_MDC 49 //!< CONN.ENET0.MDC, ADMA.I2C4.SCL, CONN.ENET1.MDC, LSIO.GPIO0.IO30
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 50 //!<
-#define SC_P_FLEXCAN0_RX 51 //!< ADMA.FLEXCAN0.RX, M40.GPIO0.IO02, LSIO.GPIO3.IO10
-#define SC_P_FLEXCAN0_TX 52 //!< ADMA.FLEXCAN0.TX, M40.GPIO0.IO03, LSIO.GPIO3.IO11
-#define SC_P_FLEXCAN1_RX 53 //!< ADMA.FLEXCAN1.RX, M40.GPIO0.IO00, ADMA.UART3.RX, LSIO.GPIO3.IO12
-#define SC_P_FLEXCAN1_TX 54 //!< ADMA.FLEXCAN1.TX, M40.GPIO0.IO01, ADMA.UART3.TX, LSIO.GPIO3.IO13
-#define SC_P_UART0_RX 55 //!< ADMA.UART0.RX, M40.UART0.RX, M40.I2C0.SCL, LSIO.GPIO3.IO14
-#define SC_P_UART0_TX 56 //!< ADMA.UART0.TX, M40.UART0.TX, M40.I2C0.SDA, LSIO.GPIO3.IO15
-#define SC_P_UART0_RTS_B 57 //!< ADMA.UART0.RTS_B, LSIO.PWM0.OUT, ADMA.UART2.RX, LSIO.GPIO3.IO16
-#define SC_P_UART0_CTS_B 58 //!< ADMA.UART0.CTS_B, LSIO.PWM1.OUT, ADMA.UART2.TX, LSIO.GPIO3.IO17
-#define SC_P_UART1_TX 59 //!< ADMA.UART1.TX, LSIO.GPT0.CLK, LSIO.PWM2.OUT, LSIO.GPIO3.IO18
-#define SC_P_UART1_RX 60 //!< ADMA.UART1.RX, LSIO.GPT0.CAPTURE, LSIO.PWM3.OUT, LSIO.GPIO3.IO19
-#define SC_P_UART1_RTS_B 61 //!< ADMA.UART1.RTS_B, LSIO.GPT0.COMPARE, ADMA.UART1.CTS_B, LSIO.GPIO3.IO20
-#define SC_P_UART1_CTS_B 62 //!< ADMA.UART1.CTS_B, ADMA.UART1.RTS_B, LSIO.GPIO3.IO21
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 63 //!<
-#define SC_P_SPI0_SCK 64 //!< ADMA.SPI0.SCK, ADMA.SAI0.RXC, LSIO.GPIO2.IO21
-#define SC_P_SPI0_SDO 65 //!< ADMA.SPI0.SDO, ADMA.SAI0.TXD, LSIO.GPIO2.IO22
-#define SC_P_SPI0_SDI 66 //!< ADMA.SPI0.SDI, ADMA.SAI0.RXD, LSIO.GPIO2.IO23
-#define SC_P_SPI0_CS0 67 //!< ADMA.SPI0.CS0, ADMA.SAI0.RXFS, LSIO.GPIO2.IO24
-#define SC_P_SPI0_CS1 68 //!< ADMA.SPI0.CS1, ADMA.SAI0.TXC, ADMA.SAI1.TXD, LSIO.GPIO2.IO25
-#define SC_P_SPI2_SCK 69 //!< ADMA.SPI2.SCK, LSIO.GPIO2.IO26
-#define SC_P_SPI2_SDO 70 //!< ADMA.SPI2.SDO, LSIO.GPIO2.IO27
-#define SC_P_SPI2_SDI 71 //!< ADMA.SPI2.SDI, LSIO.GPIO2.IO28
-#define SC_P_SPI2_CS0 72 //!< ADMA.SPI2.CS0, LSIO.GPIO2.IO29
-#define SC_P_SPI2_CS1 73 //!< ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO2.IO30
-#define SC_P_SAI1_RXC 74 //!< ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, LSIO.GPIO3.IO01
-#define SC_P_SAI1_RXD 75 //!< ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, LSIO.GPIO3.IO01
-#define SC_P_SAI1_RXFS 76 //!< ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, LSIO.GPIO3.IO02
-#define SC_P_SAI1_TXC 77 //!< ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.FLEXCAN2.RX, LSIO.GPIO3.IO03
-#define SC_P_SAI1_TXD 78 //!< ADMA.SAI1.RXD, ADMA.SAI0.TXFS, ADMA.SPI1.CS1, LSIO.GPIO3.IO04
-#define SC_P_SAI1_TXFS 79 //!< ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.FLEXCAN2.TX, LSIO.GPIO3.IO05
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 80 //!<
-#define SC_P_ESAI0_FSR 81 //!< ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RGMII_TXC
-#define SC_P_ESAI0_FST 82 //!< ADMA.ESAI0.FST, CONN.ENET1.RGMII_TX_CTL
-#define SC_P_ESAI0_SCKR 83 //!< ADMA.ESAI0.SCKR, CONN.ENET1.RGMII_TXD0
-#define SC_P_ESAI0_SCKT 84 //!< ADMA.ESAI0.SCKT, CONN.ENET1.RGMII_TXD1
-#define SC_P_ESAI0_TX0 85 //!< ADMA.ESAI0.TX0, CONN.MLB.CLK, CONN.ENET1.RGMII_TXD2
-#define SC_P_ESAI0_TX1 86 //!< ADMA.ESAI0.TX1, CONN.MLB.SIG, CONN.ENET1.RGMII_TXD3
-#define SC_P_ESAI0_TX2_RX3 87 //!< ADMA.ESAI0.TX2_RX3, CONN.MLB.DATA, CONN.ENET1.RGMII_RXC
-#define SC_P_ESAI0_TX3_RX2 88 //!< ADMA.ESAI0.TX3_RX2, CONN.ENET1.RGMII_RX_CTL
-#define SC_P_ESAI0_TX4_RX1 89 //!< ADMA.ESAI0.TX4_RX1, ADMA.MQS.R, CONN.ENET1.RGMII_RXD0
-#define SC_P_ESAI0_TX5_RX0 90 //!< ADMA.ESAI0.TX5_RX0, ADMA.MQS.L, CONN.ENET1.RGMII_RXD1
-#define SC_P_SPDIF0_RX 91 //!< ADMA.SPDIF0.RX, CONN.ENET1.RMII_RX_ER, CONN.ENET1.RGMII_RXD2
-#define SC_P_SPDIF0_TX 92 //!< ADMA.SPDIF0.TX, CONN.ENET1.RCLK50M_IN, CONN.ENET1.RGMII_RXD3
-#define SC_P_SPDIF0_EXT_CLK 93 //!< ADMA.SPDIF0.EXT_CLK, CONN.ENET1.REFCLK_125M_25M
-#define SC_P_SPI3_SCK 94 //!< ADMA.SPI3.SCK, LSIO.GPIO2.IO13
-#define SC_P_SPI3_SDO 95 //!< ADMA.SPI3.SDO, LSIO.GPIO2.IO14
-#define SC_P_SPI3_SDI 96 //!< ADMA.SPI3.SDI, ADMA.FTM.CH1, LSIO.GPIO2.IO15
-#define SC_P_SPI3_CS0 97 //!< ADMA.SPI3.CS0, ADMA.FTM.CH2, LSIO.GPIO2.IO16
-#define SC_P_SPI3_CS1 98 //!< ADMA.SPI3.CS1, ADMA.DMA0.REQ_IN0, LSIO.GPIO2.IO17
-#define SC_P_MCLK_IN0 99 //!< ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, LSIO.GPIO2.IO18
-#define SC_P_MCLK_OUT0 100 //!< ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, LSIO.GPIO2.IO19
-#define SC_P_FTM0 101 //!< ADMA.FTM.CH0, LSIO.GPIO2.IO20
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 102 //!<
-#define SC_P_ADC_IN1 103 //!< ADMA.ADC.IN1, M40.I2C0.SDA, M40.UART0.TX, LSIO.GPIO3.IO07
-#define SC_P_ADC_IN0 104 //!< ADMA.ADC.IN0, M40.I2C0.SCL, M40.UART0.RX, LSIO.GPIO3.IO06
-#define SC_P_ADC_IN3 105 //!< ADMA.ADC.IN3, M40.GPIO0.IO01, M40.TPM0.CH1, LSIO.GPIO3.IO09
-#define SC_P_ADC_IN2 106 //!< ADMA.ADC.IN2, M40.GPIO0.IO00, M40.TPM0.CH0, LSIO.GPIO3.IO08
-#define SC_P_CSI_D00 107 //!< CI_PI.D00, SNVS.TAMPER_OUT0
-#define SC_P_CSI_D01 108 //!< CI_PI.D01, SNVS.TAMPER_OUT1
-#define SC_P_CSI_D02 109 //!< CI_PI.D02, SNVS.TAMPER_OUT2
-#define SC_P_CSI_D03 110 //!< CI_PI.D03, SNVS.TAMPER_OUT3
-#define SC_P_CSI_D04 111 //!< CI_PI.D04, SNVS.TAMPER_OUT4
-#define SC_P_CSI_D05 112 //!< CI_PI.D05, SNVS.TAMPER_IN0
-#define SC_P_CSI_D06 113 //!< CI_PI.D06, SNVS.TAMPER_IN1
-#define SC_P_CSI_D07 114 //!< CI_PI.D07, SNVS.TAMPER_IN2
-#define SC_P_CSI_HSYNC 115 //!< CI_PI.HSYNC, CI_PI.D08, SNVS.TAMPER_IN3
-#define SC_P_CSI_VSYNC 116 //!< CI_PI.VSYNC, CI_PI.D09, SNVS.TAMPER_IN4
-#define SC_P_CSI_PCLK 117 //!< CI_PI.PCLK, LSIO.GPT1.CLK
-#define SC_P_CSI_MCLK 118 //!< CI_PI.MCLK
-#define SC_P_CSI_EN 119 //!< CI_PI.EN, LSIO.GPT1.CAPTURE, CI_PI.D08
-#define SC_P_CSI_RESET 120 //!< CI_PI.RESET, LSIO.GPT1.COMPARE, CI_PI.D09
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 121 //!<
-#define SC_P_PMIC_I2C_SCL 122 //!< SCU.PMIC_I2C.SCL
-#define SC_P_PMIC_I2C_SDA 123 //!< SCU.PMIC_I2C.SDA
-#define SC_P_PMIC_INT_B 124 //!< SCU.DSC.PMIC_INT_B
-#define SC_P_SCU_GPIO0_00 125 //!< SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART4.RX
-#define SC_P_SCU_GPIO0_01 126 //!< SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART4.TX
-#define SC_P_SCU_BOOT_MODE0 127 //!< SCU.DSC.BOOT_MODE0
-#define SC_P_SCU_BOOT_MODE1 128 //!< SCU.DSC.BOOT_MODE1
-#define SC_P_SCU_BOOT_MODE2 129 //!< SCU.DSC.BOOT_MODE2
-#define SC_P_SCU_BOOT_MODE3 130 //!< SCU.DSC.BOOT_MODE3
-#define SC_P_MIPI_DSI0_I2C0_SCL 131 //!< MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO4.IO00
-#define SC_P_MIPI_DSI0_I2C0_SDA 132 //!< MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO4.IO01
-#define SC_P_MIPI_DSI0_GPIO0_00 133 //!< MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO4.IO02
-#define SC_P_MIPI_DSI0_GPIO0_01 134 //!< MIPI_DSI0.GPIO0.IO01, LSIO.GPIO4.IO03
-#define SC_P_MIPI_DSI1_I2C0_SCL 135 //!< MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO4.IO04
-#define SC_P_MIPI_DSI1_I2C0_SDA 136 //!< MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO4.IO05
-#define SC_P_MIPI_DSI1_GPIO0_00 137 //!< MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO4.IO06
-#define SC_P_MIPI_DSI1_GPIO0_01 138 //!< MIPI_DSI1.GPIO0.IO01, LSIO.GPIO4.IO07
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 139 //!<
-#define SC_P_MIPI_CSI0_MCLK_OUT 140 //!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO4.IO08
-#define SC_P_MIPI_CSI0_I2C0_SCL 141 //!< MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO4.IO09
-#define SC_P_MIPI_CSI0_I2C0_SDA 142 //!< MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO4.IO10
-#define SC_P_MIPI_CSI0_GPIO0_00 143 //!< MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO4.IO11
-#define SC_P_MIPI_CSI0_GPIO0_01 144 //!< MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO4.IO12
-#define SC_P_QSPI0A_DATA0 145 //!< LSIO.QSPI0A.DATA0, MIPI_DSI0.I2C0.SCL
-#define SC_P_QSPI0A_DATA1 146 //!< LSIO.QSPI0A.DATA1, MIPI_DSI0.I2C0.SDA
-#define SC_P_QSPI0A_DATA2 147 //!< LSIO.QSPI0A.DATA2, MIPI_DSI1.I2C0.SCL
-#define SC_P_QSPI0A_DATA3 148 //!< LSIO.QSPI0A.DATA3, MIPI_DSI1.I2C0.SDA
-#define SC_P_QSPI0A_DQS 149 //!< LSIO.QSPI0A.DQS
-#define SC_P_QSPI0A_SS0_B 150 //!< LSIO.QSPI0A.SS0_B, MIPI_CSI0.I2C0.SCL
-#define SC_P_QSPI0A_SS1_B 151 //!< LSIO.QSPI0A.SS1_B, MIPI_CSI0.I2C0.SDA
-#define SC_P_QSPI0A_SCLK 152 //!< LSIO.QSPI0A.SCLK
-#define SC_P_QSPI0B_SCLK 153 //!< LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0
-#define SC_P_QSPI0B_DATA0 154 //!< LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1
-#define SC_P_QSPI0B_DATA1 155 //!< LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2
-#define SC_P_QSPI0B_DATA2 156 //!< LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3
-#define SC_P_QSPI0B_DATA3 157 //!< LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0
-#define SC_P_QSPI0B_DQS 158 //!< LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1
-#define SC_P_QSPI0B_SS0_B 159 //!< LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2
-#define SC_P_QSPI0B_SS1_B 160 //!< LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 161 //!<
-#define SC_P_XTALI 162 //!< SCU.DSC.XTALI
-#define SC_P_XTALO 163 //!< SCU.DSC.XTALO
-#define SC_P_ANA_TEST_OUT_P 164 //!< SCU.DSC.TEST_OUT_P
-#define SC_P_ANA_TEST_OUT_N 165 //!< SCU.DSC.TEST_OUT_N
-#define SC_P_RTC_XTALI 166 //!< SNVS.RTC_XTALI
-#define SC_P_RTC_XTALO 167 //!< SNVS.RTC_XTALO
-#define SC_P_PMIC_ON_REQ 168 //!< SNVS.PMIC_ON_REQ
-#define SC_P_ON_OFF_BUTTON 169 //!< SNVS.ON_OFF_BUTTON
+#define SC_P_PCIE_CTRL0_PERST_B 0 /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */
+#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */
+#define SC_P_PCIE_CTRL0_WAKE_B 2 /* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /* */
+#define SC_P_USB_SS3_TC0 4 /* ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */
+#define SC_P_USB_SS3_TC1 5 /* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
+#define SC_P_USB_SS3_TC2 6 /* ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */
+#define SC_P_USB_SS3_TC3 7 /* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 /* */
+#define SC_P_EMMC0_CLK 9 /* CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */
+#define SC_P_EMMC0_CMD 10 /* CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */
+#define SC_P_EMMC0_DATA0 11 /* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */
+#define SC_P_EMMC0_DATA1 12 /* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */
+#define SC_P_EMMC0_DATA2 13 /* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */
+#define SC_P_EMMC0_DATA3 14 /* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 /* */
+#define SC_P_EMMC0_DATA4 16 /* CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */
+#define SC_P_EMMC0_DATA5 17 /* CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */
+#define SC_P_EMMC0_DATA6 18 /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */
+#define SC_P_EMMC0_DATA7 19 /* CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */
+#define SC_P_EMMC0_STROBE 20 /* CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */
+#define SC_P_EMMC0_RESET_B 21 /* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 /* */
+#define SC_P_USDHC1_RESET_B 23 /* CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */
+#define SC_P_USDHC1_VSELECT 24 /* CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */
+#define SC_P_CTL_NAND_RE_P_N 25 /* */
+#define SC_P_USDHC1_WP 26 /* CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */
+#define SC_P_USDHC1_CD_B 27 /* CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */
+#define SC_P_CTL_NAND_DQS_P_N 28 /* */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 /* */
+#define SC_P_USDHC1_CLK 30 /* CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */
+#define SC_P_USDHC1_CMD 31 /* CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */
+#define SC_P_USDHC1_DATA0 32 /* CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */
+#define SC_P_USDHC1_DATA1 33 /* CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */
+#define SC_P_USDHC1_DATA2 34 /* CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */
+#define SC_P_USDHC1_DATA3 35 /* CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 /* */
+#define SC_P_ENET0_RGMII_TXC 37 /* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */
+#define SC_P_ENET0_RGMII_TX_CTL 38 /* CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */
+#define SC_P_ENET0_RGMII_TXD0 39 /* CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */
+#define SC_P_ENET0_RGMII_TXD1 40 /* CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */
+#define SC_P_ENET0_RGMII_TXD2 41 /* CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */
+#define SC_P_ENET0_RGMII_TXD3 42 /* CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 /* */
+#define SC_P_ENET0_RGMII_RXC 44 /* CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */
+#define SC_P_ENET0_RGMII_RX_CTL 45 /* CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */
+#define SC_P_ENET0_RGMII_RXD0 46 /* CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */
+#define SC_P_ENET0_RGMII_RXD1 47 /* CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */
+#define SC_P_ENET0_RGMII_RXD2 48 /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */
+#define SC_P_ENET0_RGMII_RXD3 49 /* CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 /* */
+#define SC_P_ENET0_REFCLK_125M_25M 51 /* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */
+#define SC_P_ENET0_MDIO 52 /* CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */
+#define SC_P_ENET0_MDC 53 /* CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 /* */
+#define SC_P_ESAI0_FSR 55 /* ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */
+#define SC_P_ESAI0_FST 56 /* ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */
+#define SC_P_ESAI0_SCKR 57 /* ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */
+#define SC_P_ESAI0_SCKT 58 /* ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */
+#define SC_P_ESAI0_TX0 59 /* ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */
+#define SC_P_ESAI0_TX1 60 /* ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */
+#define SC_P_ESAI0_TX2_RX3 61 /* ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */
+#define SC_P_ESAI0_TX3_RX2 62 /* ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */
+#define SC_P_ESAI0_TX4_RX1 63 /* ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */
+#define SC_P_ESAI0_TX5_RX0 64 /* ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */
+#define SC_P_SPDIF0_RX 65 /* ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */
+#define SC_P_SPDIF0_TX 66 /* ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */
+#define SC_P_SPDIF0_EXT_CLK 67 /* ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 /* */
+#define SC_P_SPI3_SCK 69 /* ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */
+#define SC_P_SPI3_SDO 70 /* ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */
+#define SC_P_SPI3_SDI 71 /* ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */
+#define SC_P_SPI3_CS0 72 /* ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */
+#define SC_P_SPI3_CS1 73 /* ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */
+#define SC_P_MCLK_IN1 74 /* ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */
+#define SC_P_MCLK_IN0 75 /* ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */
+#define SC_P_MCLK_OUT0 76 /* ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */
+#define SC_P_UART1_TX 77 /* ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */
+#define SC_P_UART1_RX 78 /* ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */
+#define SC_P_UART1_RTS_B 79 /* ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */
+#define SC_P_UART1_CTS_B 80 /* ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 /* */
+#define SC_P_SAI0_TXD 82 /* ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */
+#define SC_P_SAI0_TXC 83 /* ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */
+#define SC_P_SAI0_RXD 84 /* ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */
+#define SC_P_SAI0_TXFS 85 /* ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */
+#define SC_P_SAI1_RXD 86 /* ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */
+#define SC_P_SAI1_RXC 87 /* ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */
+#define SC_P_SAI1_RXFS 88 /* ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */
+#define SC_P_SPI2_CS0 89 /* ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */
+#define SC_P_SPI2_SDO 90 /* ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */
+#define SC_P_SPI2_SDI 91 /* ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */
+#define SC_P_SPI2_SCK 92 /* ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */
+#define SC_P_SPI0_SCK 93 /* ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */
+#define SC_P_SPI0_SDI 94 /* ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */
+#define SC_P_SPI0_SDO 95 /* ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */
+#define SC_P_SPI0_CS1 96 /* ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */
+#define SC_P_SPI0_CS0 97 /* ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 /* */
+#define SC_P_ADC_IN1 99 /* ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */
+#define SC_P_ADC_IN0 100 /* ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */
+#define SC_P_ADC_IN3 101 /* ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */
+#define SC_P_ADC_IN2 102 /* ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */
+#define SC_P_ADC_IN5 103 /* ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */
+#define SC_P_ADC_IN4 104 /* ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */
+#define SC_P_FLEXCAN0_RX 105 /* ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */
+#define SC_P_FLEXCAN0_TX 106 /* ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */
+#define SC_P_FLEXCAN1_RX 107 /* ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */
+#define SC_P_FLEXCAN1_TX 108 /* ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */
+#define SC_P_FLEXCAN2_RX 109 /* ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */
+#define SC_P_FLEXCAN2_TX 110 /* ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */
+#define SC_P_UART0_RX 111 /* ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, LSIO.GPIO1.IO21 */
+#define SC_P_UART0_TX 112 /* ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, LSIO.GPIO1.IO22 */
+#define SC_P_UART2_TX 113 /* ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */
+#define SC_P_UART2_RX 114 /* ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 /* */
+#define SC_P_MIPI_DSI0_I2C0_SCL 116 /* MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */
+#define SC_P_MIPI_DSI0_I2C0_SDA 117 /* MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */
+#define SC_P_MIPI_DSI0_GPIO0_00 118 /* MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */
+#define SC_P_MIPI_DSI0_GPIO0_01 119 /* MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */
+#define SC_P_MIPI_DSI1_I2C0_SCL 120 /* MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */
+#define SC_P_MIPI_DSI1_I2C0_SDA 121 /* MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */
+#define SC_P_MIPI_DSI1_GPIO0_00 122 /* MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */
+#define SC_P_MIPI_DSI1_GPIO0_01 123 /* MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 /* */
+#define SC_P_JTAG_TRST_B 125 /* SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */
+#define SC_P_PMIC_I2C_SCL 126 /* SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */
+#define SC_P_PMIC_I2C_SDA 127 /* SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */
+#define SC_P_PMIC_INT_B 128 /* SCU.DSC.PMIC_INT_B */
+#define SC_P_SCU_GPIO0_00 129 /* SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */
+#define SC_P_SCU_GPIO0_01 130 /* SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */
+#define SC_P_SCU_PMIC_STANDBY 131 /* SCU.DSC.PMIC_STANDBY */
+#define SC_P_SCU_BOOT_MODE0 132 /* SCU.DSC.BOOT_MODE0 */
+#define SC_P_SCU_BOOT_MODE1 133 /* SCU.DSC.BOOT_MODE1 */
+#define SC_P_SCU_BOOT_MODE2 134 /* SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */
+#define SC_P_SCU_BOOT_MODE3 135 /* SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */
+#define SC_P_CSI_D00 136 /* CI_PI.D02, ADMA.SAI0.RXC */
+#define SC_P_CSI_D01 137 /* CI_PI.D03, ADMA.SAI0.RXD */
+#define SC_P_CSI_D02 138 /* CI_PI.D04, ADMA.SAI0.RXFS */
+#define SC_P_CSI_D03 139 /* CI_PI.D05, ADMA.SAI2.RXC */
+#define SC_P_CSI_D04 140 /* CI_PI.D06, ADMA.SAI2.RXD */
+#define SC_P_CSI_D05 141 /* CI_PI.D07, ADMA.SAI2.RXFS */
+#define SC_P_CSI_D06 142 /* CI_PI.D08, ADMA.SAI3.RXC */
+#define SC_P_CSI_D07 143 /* CI_PI.D09, ADMA.SAI3.RXD */
+#define SC_P_CSI_HSYNC 144 /* CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */
+#define SC_P_CSI_VSYNC 145 /* CI_PI.VSYNC, CI_PI.D01 */
+#define SC_P_CSI_PCLK 146 /* CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */
+#define SC_P_CSI_MCLK 147 /* CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */
+#define SC_P_CSI_EN 148 /* CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */
+#define SC_P_CSI_RESET 149 /* CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 /* */
+#define SC_P_MIPI_CSI0_MCLK_OUT 151 /* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */
+#define SC_P_MIPI_CSI0_I2C0_SCL 152 /* MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */
+#define SC_P_MIPI_CSI0_I2C0_SDA 153 /* MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */
+#define SC_P_MIPI_CSI0_GPIO0_01 154 /* MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */
+#define SC_P_MIPI_CSI0_GPIO0_00 155 /* MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */
+#define SC_P_QSPI0A_DATA0 156 /* LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */
+#define SC_P_QSPI0A_DATA1 157 /* LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */
+#define SC_P_QSPI0A_DATA2 158 /* LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */
+#define SC_P_QSPI0A_DATA3 159 /* LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */
+#define SC_P_QSPI0A_DQS 160 /* LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */
+#define SC_P_QSPI0A_SS0_B 161 /* LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */
+#define SC_P_QSPI0A_SS1_B 162 /* LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */
+#define SC_P_QSPI0A_SCLK 163 /* LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 /* */
+#define SC_P_QSPI0B_SCLK 165 /* LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */
+#define SC_P_QSPI0B_DATA0 166 /* LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */
+#define SC_P_QSPI0B_DATA1 167 /* LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */
+#define SC_P_QSPI0B_DATA2 168 /* LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */
+#define SC_P_QSPI0B_DATA3 169 /* LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */
+#define SC_P_QSPI0B_DQS 170 /* LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */
+#define SC_P_QSPI0B_SS0_B 171 /* LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */
+#define SC_P_QSPI0B_SS1_B 172 /* LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 /* */
/*@}*/
-#endif /* _SC_PINS_H */
-
+#endif /* _SC_PINS_H */
#define SC_R_CAAM_JR1_OUT 514
#define SC_R_CAAM_JR2_OUT 515
#define SC_R_CAAM_JR3_OUT 516
-#define SC_R_LAST 517
+#define SC_R_VPU_DEC 517
+#define SC_R_VPU_ENC 518
+#define SC_R_CAAM_JR0 519
+#define SC_R_CAAM_JR0_OUT 520
+#define SC_R_PMIC_2 521
+#define SC_R_LAST 522
#endif /* __DT_BINDINGS_RSCRC_IMX_H */
SC_IRQ_TEMP_VPU_LOW = (1 << 17), /* DRC1 temp alarm interrupt */
SC_IRQ_TEMP_PMIC0_LOW = (1 << 18), /* PMIC0 temp alarm interrupt */
SC_IRQ_TEMP_PMIC1_LOW = (1 << 19), /* PMIC1 temp alarm interrupt */
+ SC_IRQ_TEMP_PMIC2_HIGH = (1 << 20), /* PMIC2 temp alarm interrupt */
+ SC_IRQ_TEMP_PMIC2_LOW = (1 << 21) /* PMIC2 temp alarm interrupt */
} sc_irq_temp_t;
/*!
/* Functions */
+/*!
+ * @name Control Functions
+ * @{
+ */
+
/*!
* This function sets a miscellaneous control value.
*
sc_err_t sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource,
sc_ctrl_t ctrl, uint32_t *val);
+/* @} */
+
/*!
- * This function configures the ARI match value for PCIe/SATA resources.
- *
- * @param[in] ipc IPC handle
- * @param[in] resource match resource
- * @param[in] resource_mst PCIe/SATA master to match
- * @param[in] ari ARI to match
- * @param[in] enable enable match or not
- *
- * @return Returns an error code (SC_ERR_NONE = success).
- *
- * Return errors:
- * - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the owner or parent
- * of the owner of the resource and translation
- *
- * For PCIe, the ARI is the 16-bit value that includes the bus number,
- * device number, and function number. For SATA, this value includes the
- * FISType and PM_Port.
+ * @name DMA Functions
+ * @{
*/
-sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource,
- sc_rsrc_t resource_mst, uint16_t ari, bool enable);
/*!
* This function configures the max DMA channel priority group for a
sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource,
sc_misc_dma_group_t group);
-/*!
- * This function starts/stops emulation waveform capture.
- *
- * @param[in] ipc IPC handle
- * @param[in] enable flag to enable/disable capture
- *
- * @return Returns an error code (SC_ERR_NONE = success).
- *
- * Return errors:
- * - SC_ERR_UNAVAILABLE if not running on emulation
- */
-sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, bool enable);
+/* @} */
/*!
- * This function reports boot status.
- *
- * @param[in] ipc IPC handle
- * @param[in] status boot status
- *
- * This is used by SW partitions to report status of boot. This is
- * normally used to report a boot failure.
+ * @name Security Functions
+ * @{
*/
-void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status);
/*!
* This function loads a SECO image.
sc_misc_seco_auth_cmd_t cmd,
uint32_t addr_meta);
+/* @} */
+
+/*!
+ * @name Debug Functions
+ * @{
+ */
+
+/*!
+ * This function is used output a debug character from the SCU UART.
+ *
+ * @param[in] ipc IPC handle
+ * @param[in] ch character to output
+ */
+void sc_misc_debug_out(sc_ipc_t ipc, uint8_t ch);
+
+/*!
+ * This function starts/stops waveform capture.
+ *
+ * @param[in] ipc IPC handle
+ * @param[in] enable flag to enable/disable capture
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_UNAVAILABLE if not running
+ */
+sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, bool enable);
+
+/* @} */
+
+/*!
+ * @name Other Functions
+ * @{
+ */
+
+/*!
+ * This function configures the ARI match value for PCIe/SATA resources.
+ *
+ * @param[in] ipc IPC handle
+ * @param[in] resource match resource
+ * @param[in] resource_mst PCIe/SATA master to match
+ * @param[in] ari ARI to match
+ * @param[in] enable enable match or not
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the owner or parent
+ * of the owner of the resource and translation
+ *
+ * For PCIe, the ARI is the 16-bit value that includes the bus number,
+ * device number, and function number. For SATA, this value includes the
+ * FISType and PM_Port.
+ */
+sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource,
+ sc_rsrc_t resource_mst, uint16_t ari, bool enable);
+
+/*!
+ * This function reports boot status.
+ *
+ * @param[in] ipc IPC handle
+ * @param[in] status boot status
+ *
+ * This is used by SW partitions to report status of boot. This is
+ * normally used to report a boot failure.
+ */
+void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status);
+
+/* @} */
+
#endif /* _SC_MISC_API_H */
/**@}*/
*/
typedef enum sc_pad_28fdsio_dse_e {
SC_PAD_28FDSOI_DSE_18V_1MA = 0, /* Drive strength of 1mA for 1.8v */
- SC_PAD_28FDSOI_DSE_33V_2MA = 0, /* Drive strength of 2mA for 3.3v */
- SC_PAD_28FDSOI_DSE_DV_HIGH = 0, /* Drive strength of 12mA for dual volt */
SC_PAD_28FDSOI_DSE_18V_2MA = 1, /* Drive strength of 2mA for 1.8v */
- SC_PAD_28FDSOI_DSE_33V_4MA = 1, /* Drive strength of 4mA for 3.3v */
- SC_PAD_28FDSOI_DSE_DV_LOW = 1, /* Drive strength of 12mA for dual volt */
SC_PAD_28FDSOI_DSE_18V_4MA = 2, /* Drive strength of 4mA for 1.8v */
- SC_PAD_28FDSOI_DSE_33V_8MA = 2, /* Drive strength of 8mA for 3.3v */
SC_PAD_28FDSOI_DSE_18V_6MA = 3, /* Drive strength of 6mA for 1.8v */
- SC_PAD_28FDSOI_DSE_33V_12MA = 3, /* Drive strength of 12mA for 3.3v */
SC_PAD_28FDSOI_DSE_18V_8MA = 4, /* Drive strength of 8mA for 1.8v */
SC_PAD_28FDSOI_DSE_18V_10MA = 5, /* Drive strength of 10mA for 1.8v */
SC_PAD_28FDSOI_DSE_18V_12MA = 6, /* Drive strength of 12mA for 1.8v */
- SC_PAD_28FDSOI_DSE_33V_HS = 7 /* High-speed drive strength for 1.8v */
+ SC_PAD_28FDSOI_DSE_33V_2MA = 0, /* Drive strength of 2mA for 3.3v */
+ SC_PAD_28FDSOI_DSE_33V_4MA = 1, /* Drive strength of 4mA for 3.3v */
+ SC_PAD_28FDSOI_DSE_33V_8MA = 2, /* Drive strength of 8mA for 3.3v */
+ SC_PAD_28FDSOI_DSE_33V_12MA = 3, /* Drive strength of 12mA for 3.3v */
+ SC_PAD_28FDSOI_DSE_33V_HS = 7, /* High-speed drive strength for 1.8v */
+ SC_PAD_28FDSOI_DSE_DV_LOW = 0, /* Low drive strength for dual volt */
+ SC_PAD_28FDSOI_DSE_DV_HIGH = 1 /* High drive strength for dual volt */
} sc_pad_28fdsoi_dse_t;
/*!
/* Functions */
+/*!
+ * @name Generic Functions
+ * @{
+ */
+
/*!
* This function configures the mux settings for a pin. This includes
* the signal mux, pad config, and low-power isolation mode.
sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pin_t pin,
uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso);
+/*!
+ * This function gets the mux settings for a pin. This includes
+ * the signal mux, pad config, and low-power isolation mode.
+ *
+ * @param[in] ipc IPC handle
+ * @param[in] pin pin to query
+ * @param[out] mux pointer to return mux setting
+ * @param[out] config pointer to return pad config
+ * @param[out] iso pointer to return low-power isolation mode
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ *
+ * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ */
+sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pin_t pin,
+ uint8_t *mux, sc_pad_config_t *config,
+ sc_pad_iso_t *iso);
+
/*!
* This function configures the general purpose pad control. This
* is technology dependent and includes things like drive strength,
sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pin_t pin, uint32_t ctrl);
/*!
- * This function configures the pad control specific to 28LPP.
+ * This function gets the general purpose pad control. This
+ * is technology dependent and includes things like drive strength,
+ * slew rate, pull up/down, etc. Refer to the SoC Reference Manual
+ * for bit field details.
*
* @param[in] ipc IPC handle
- * @param[in] pin pin to configure
- * @param[in] dse drive strength
- * @param[in] sre slew rate
- * @param[in] hys hysteresis
- * @param[in] pe pull enable
- * @param[in] ps pull select
+ * @param[in] pin pin to query
+ * @param[out] ctrl pointer to return control value
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner,
- * - SC_ERR_UNAVAILABLE if process not applicable
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner
*
* Refer to the SoC [Pin List](@ref PINS) for valid pin values.
*/
-sc_err_t sc_pad_set_gp_28lpp(sc_ipc_t ipc, sc_pin_t pin,
- sc_pad_28lpp_dse_t dse, bool sre, bool hys,
- bool pe, sc_pad_28lpp_ps_t ps);
+sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pin_t pin, uint32_t *ctrl);
/*!
* This function configures the wakeup mode of the pin.
*/
sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pin_t pin, sc_pad_wakeup_t wakeup);
+/*!
+ * This function gets the wakeup mode of a pin.
+ *
+ * @param[in] ipc IPC handle
+ * @param[in] pin pin to query
+ * @param[out] wakeup pointer to return wakeup
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid,
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ *
+ * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
+ */
+sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pin_t pin, sc_pad_wakeup_t *wakeup);
+
/*!
* This function configures a pad.
*
sc_pad_wakeup_t wakeup);
/*!
- * This function gets the mux settings for a pin. This includes
- * the signal mux, pad config, and low-power isolation mode.
+ * This function gets a pad's config.
*
* @param[in] ipc IPC handle
* @param[in] pin pin to query
* @param[out] mux pointer to return mux setting
* @param[out] config pointer to return pad config
* @param[out] iso pointer to return low-power isolation mode
+ * @param[out] ctrl pointer to return control value
+ * @param[out] wakeup pointer to return wakeup to set
*
- * @return Returns an error code (SC_ERR_NONE = success).
+ * @see sc_pad_set_mux().
+ * @see sc_pad_set_gp().
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the pin owner
*
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
* Refer to the SoC [Pin List](@ref PINS) for valid pin values.
*/
-sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pin_t pin,
- uint8_t *mux, sc_pad_config_t *config,
- sc_pad_iso_t *iso);
+sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pin_t pin, uint8_t *mux,
+ sc_pad_config_t *config, sc_pad_iso_t *iso,
+ uint32_t *ctrl, sc_pad_wakeup_t *wakeup);
+
+/* @} */
/*!
- * This function gets the general purpose pad control. This
- * is technology dependent and includes things like drive strength,
- * slew rate, pull up/down, etc. Refer to the SoC Reference Manual
- * for bit field details.
+ * @name SoC Specific Functions
+ * @{
+ */
+
+/*!
+ * This function configures the settings for a pin. This setting is SoC
+ * specific.
*
* @param[in] ipc IPC handle
- * @param[in] pin pin to query
- * @param[out] ctrl pointer to return control value
+ * @param[in] pin pin to configure
+ * @param[in] val value to set
*
* @return Returns an error code (SC_ERR_NONE = success).
*
*
* Refer to the SoC [Pin List](@ref PINS) for valid pin values.
*/
-sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pin_t pin, uint32_t *ctrl);
+sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pin_t pin, uint32_t val);
/*!
- * This function gets the pad control specific to 28LPP.
+ * This function gets the settings for a pin. This setting is SoC
+ * specific.
*
* @param[in] ipc IPC handle
* @param[in] pin pin to query
- * @param[out] dse pointer to return drive strength
- * @param[out] sre pointer to return slew rate
- * @param[out] hys pointer to return hysteresis
- * @param[out] pe pointer to return pull enable
- * @param[out] ps pointer to return pull select
+ * @param[out] val pointer to return setting
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner,
- * - SC_ERR_UNAVAILABLE if process not applicable
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner
*
* Refer to the SoC [Pin List](@ref PINS) for valid pin values.
*/
-sc_err_t sc_pad_get_gp_28lpp(sc_ipc_t ipc, sc_pin_t pin,
- sc_pad_28lpp_dse_t *dse, bool *sre, bool *hys,
- bool *pe, sc_pad_28lpp_ps_t *ps);
+sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pin_t pin, uint32_t *val);
+
+/* @} */
/*!
- * This function gets the wakeup mode of a pin.
+ * @name Technology Specific Functions
+ * @{
+ */
+
+/*!
+ * This function configures the pad control specific to 28LPP.
*
* @param[in] ipc IPC handle
- * @param[in] pin pin to query
- * @param[out] wakeup pointer to return wakeup
+ * @param[in] pin pin to configure
+ * @param[in] dse drive strength
+ * @param[in] sre slew rate
+ * @param[in] hys hysteresis
+ * @param[in] pe pull enable
+ * @param[in] ps pull select
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner,
+ * - SC_ERR_UNAVAILABLE if process not applicable
*
* Refer to the SoC [Pin List](@ref PINS) for valid pin values.
*/
-sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pin_t pin,
- sc_pad_wakeup_t *wakeup);
+sc_err_t sc_pad_set_gp_28lpp(sc_ipc_t ipc, sc_pin_t pin,
+ sc_pad_28lpp_dse_t dse, bool sre, bool hys,
+ bool pe, sc_pad_28lpp_ps_t ps);
/*!
- * This function gets a pad's config.
+ * This function gets the pad control specific to 28LPP.
*
* @param[in] ipc IPC handle
* @param[in] pin pin to query
- * @param[out] mux pointer to return mux setting
- * @param[out] config pointer to return pad config
- * @param[out] iso pointer to return low-power isolation mode
- * @param[out] ctrl pointer to return control value
- * @param[out] wakeup pointer to return wakeup to set
+ * @param[out] dse pointer to return drive strength
+ * @param[out] sre pointer to return slew rate
+ * @param[out] hys pointer to return hysteresis
+ * @param[out] pe pointer to return pull enable
+ * @param[out] ps pointer to return pull select
*
- * @see sc_pad_set_mux().
- * @see sc_pad_set_gp().
+ * @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner
- *
- * @return Returns an error code (SC_ERR_NONE = success).
+ * - SC_ERR_NOACCESS if caller's partition is not the pin owner,
+ * - SC_ERR_UNAVAILABLE if process not applicable
*
* Refer to the SoC [Pin List](@ref PINS) for valid pin values.
*/
-sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pin_t pin, uint8_t *mux,
- sc_pad_config_t *config, sc_pad_iso_t *iso,
- uint32_t *ctrl, sc_pad_wakeup_t *wakeup);
+sc_err_t sc_pad_get_gp_28lpp(sc_ipc_t ipc, sc_pin_t pin,
+ sc_pad_28lpp_dse_t *dse, bool *sre, bool *hys,
+ bool *pe, sc_pad_28lpp_ps_t *ps);
/*!
* This function configures the pad control specific to 28FDSOI.
bool *nasrc_sel, bool *compok,
uint8_t *nasrc);
-/*!
- * This function configures the settings for a pin. This setting is SoC
- * specific.
- *
- * @param[in] ipc IPC handle
- * @param[in] pin pin to configure
- * @param[in] val value to set
- *
- * @return Returns an error code (SC_ERR_NONE = success).
- *
- * Return errors:
- * - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner
- *
- * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
- */
-sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pin_t pin, uint32_t val);
-
-/*!
- * This function gets the settings for a pin. This setting is SoC
- * specific.
- *
- * @param[in] ipc IPC handle
- * @param[in] pin pin to query
- * @param[out] val pointer to return setting
- *
- * @return Returns an error code (SC_ERR_NONE = success).
- *
- * Return errors:
- * - SC_PARM if arguments out of range or invalid,
- * - SC_ERR_NOACCESS if caller's partition is not the pin owner
- *
- * Refer to the SoC [Pin List](@ref PINS) for valid pin values.
- */
-sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pin_t pin, uint32_t *val);
+/* @} */
#endif /* _SC_PAD_API_H */
* This type is used to declare a clock mode.
*/
typedef enum sc_pm_clk_mode_e {
- SC_PM_CLK_MODE_OFF = 0, /* Clock is disabled */
- SC_PM_CLK_MODE_ON = 1, /* Clock is enabled. */
- SC_PM_CLK_MODE_AUTOGATE_SW = 2, /* Clock is in SW autogate mode */
- SC_PM_CLK_MODE_AUTOGATE_HW = 3, /* Clock is in HW autogate mode */
- SC_PM_CLK_MODE_AUTOGATE_SW_HW = 4, /* Clock is in SW-HW autogate mode */
+ SC_PM_CLK_MODE_ROM_INIT = 0,
+ SC_PM_CLK_MODE_OFF = 1, /* Clock is disabled */
+ SC_PM_CLK_MODE_ON = 2, /* Clock is enabled. */
+ SC_PM_CLK_MODE_AUTOGATE_SW = 3, /* Clock is in SW autogate mode */
+ SC_PM_CLK_MODE_AUTOGATE_HW = 4, /* Clock is in HW autogate mode */
+ SC_PM_CLK_MODE_AUTOGATE_SW_HW = 5, /* Clock is in SW-HW autogate mode */
} sc_pm_clk_mode_t;
/*!
* @{
*/
+/*!
+ * This function is used to reset the system. Only the owner of the
+ * SC_R_SYSTEM resource can do this.
+ *
+ * @param[in] ipc IPC handle
+ * @param[in] type reset type
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid type
+ *
+ * If this function returns, then the reset did not occur due to an
+ * invalid parameter.
+ */
+sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type);
+
+/*!
+ * This function gets a caller's reset reason.
+ *
+ * @param[in] ipc IPC handle
+ * @param[out] reason pointer to return reset reason
+ */
+sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason);
+
/*!
* This function is used to boot a partition.
*
*/
void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type);
-/*!
- * This function gets a caller's reset reason.
- *
- * @param[in] ipc IPC handle
- * @param[out] reason pointer to return reset reason
- */
-sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason);
-
-/*!
- * This function is used to start/stop a CPU.
- *
- * @param[in] ipc IPC handle
- * @param[in] resource ID of the CPU resource
- * @param[in] enable start if true; otherwise stop
- * @param[in] address 64-bit boot address
- *
- * @return Returns an error code (SC_ERR_NONE = success).
- *
- * Return errors:
- * - SC_ERR_PARM if invalid resource or address,
- * - SC_ERR_NOACCESS if caller's partition is not the parent of the
- * resource (CPU) owner
- */
-sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, bool enable,
- sc_faddr_t address);
-
/*!
* This function is used to reboot a partition.
*
sc_pm_reset_type_t type);
/*!
- * This function is used to reset the system. Only the owner of the
- * SC_R_SYSTEM resource can do this.
+ * This function is used to start/stop a CPU.
*
* @param[in] ipc IPC handle
- * @param[in] type reset type
+ * @param[in] resource ID of the CPU resource
+ * @param[in] enable start if true; otherwise stop
+ * @param[in] address 64-bit boot address
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
- * - SC_ERR_PARM if invalid type
- *
- * If this function returns, then the reset did not occur due to an
- * invalid parameter.
+ * - SC_ERR_PARM if invalid resource or address,
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of the
+ * resource (CPU) owner
*/
-sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type);
+sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, bool enable,
+ sc_faddr_t address);
/* @} */
uint8_t *day, uint8_t *hour, uint8_t *min,
uint8_t *sec);
+/*!
+ * This function gets the RTC time in seconds since 1/1/1970.
+ *
+ * @param[in] ipc IPC handle
+ * @param[out] sec pointer to return second
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ */
+sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec);
+
/*!
* This function sets the RTC alarm. Only the owner of the SC_R_SYSTEM
* resource can set the alarm.
uint8_t day, uint8_t hour, uint8_t min,
uint8_t sec);
-/*!
- * This function gets the RTC time in seconds since 1/1/1970.
- *
- * @param[in] ipc IPC handle
- * @param[out] sec pointer to return second
- *
- * @return Returns an error code (SC_ERR_NONE = success).
- */
-sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec);
-
/* @} */
#endif /* _SC_TIMER_API_H */
SC_R_CAAM_JR1_OUT = 514,
SC_R_CAAM_JR2_OUT = 515,
SC_R_CAAM_JR3_OUT = 516,
+ SC_R_VPU_DEC = 517,
+ SC_R_VPU_ENC = 518,
+ SC_R_CAAM_JR0 = 519,
+ SC_R_CAAM_JR0_OUT = 520,
+ SC_R_PMIC_2 = 521,
SC_R_LAST
} sc_rsrc_t;
SC_C_SYNC_CTRL1 = 33,
SC_C_DPI_RESET = 34,
SC_C_MIPI_RESET = 35,
+ SC_C_DUAL_MODE = 36,
SC_C_LAST
} sc_ctrl_t;
projects / linux.git / commitdiff