SHE-17 arm64: dts: imx8qm: enable first SECO MU

Enabling use of the first SECO MU on i.MX8QM

Signed-off-by: Stephane Dion <stephane.dion_1@nxp.com>
(cherry picked from commit 2b65b323254965b1d563e0aee80e18678d631b9d)

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
index f4d9852..01236e4 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
@@ -329,6 +329,32 @@
                        };
                };
 
+               pd_seco_mu: PD_SECO_MU {
+                       compatible = "nxp,imx8-pd";
+                       reg = <SC_R_NONE>;
+                       #power-domain-cells = <0>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       pd_seco_mu_2: PD_SECO_MU_2 {
+                               reg = <SC_R_SECO_MU_2>;
+                               #power-domain-cells = <0>;
+                               power-domains = <&pd_seco_mu>;
+                       };
+
+                       pd_seco_mu_3: PD_SECO_MU_3 {
+                               reg = <SC_R_SECO_MU_3>;
+                               #power-domain-cells = <0>;
+                               power-domains = <&pd_seco_mu>;
+                       };
+
+                       pd_seco_mu_4: PD_SECO_MU_4 {
+                               reg = <SC_R_SECO_MU_4>;
+                               #power-domain-cells = <0>;
+                               power-domains = <&pd_seco_mu>;
+                       };
+               };
+
                pd_conn: PD_CONN {
                        compatible = "nxp,imx8-pd";
                        reg = <SC_R_NONE>;

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
index ecac333..33d4540 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
@@ -154,6 +154,30 @@
                status = "okay";
        };
 
+       mu_seco2: mu@31560000 {
+               compatible = "fsl,imx8-seco-mu";
+               reg = <0x0 0x31560000 0x0 0x10000>;
+               power-domains = <&pd_seco_mu_2>;
+               interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>;
+               status = "okay";
+       };
+
+       mu_seco3: mu@31570000 {
+               compatible = "fsl,imx8-seco-mu";
+               reg = <0x0 0x31570000 0x0 0x10000>;
+               power-domains = <&pd_seco_mu_3>;
+               interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
+       mu_seco4: mu@31580000 {
+               compatible = "fsl,imx8-seco-mu";
+               reg = <0x0 0x31580000 0x0 0x10000>;
+               power-domains = <&pd_seco_mu_4>;
+               interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
        mu13: mu13@5d280000 {
                compatible = "fsl,imx8-mu-dsp";
                reg = <0x0 0x5d280000 0x0 0x10000>;