MLK-13361-3 arm: imx6q: busfreq: restore mmdc timing settings for 100MHz

The timing settings for 100MHz are almost the same as the ones for
400MHz except for the MMDCx_MISC[RALAT] parameter which needs to be
set to 2 cycles.

For the 100MHz case the restoration of the mmdc setting should be performed
in 2 steps: restore the mmdc setting and then overwrite the RALAT setting
for 2 cycles.

A decision code within the "mmdc_clk_lower_equal_100MHz" macro is added
to go to the "equal to 100MHz" or to the "lower to 100MHz" case

Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
Signed-off-by: Alejandro Lozano <alejandro.lozano@nxp.com>

diff --git a/arch/arm/mach-imx/lpddr2_freq_imx6q.S b/arch/arm/mach-imx/lpddr2_freq_imx6q.S
index e14920d..593363a 100644 (file)
--- a/arch/arm/mach-imx/lpddr2_freq_imx6q.S
+++ b/arch/arm/mach-imx/lpddr2_freq_imx6q.S
@@ -227,7 +227,17 @@ skip_below_100Mhz_ch1_timings:
 
        .macro  mmdc_clk_lower_equal_100MHz
 
+       ldr     r10, =100000000
+       cmp     r0, r10
+       beq     set_timmings_100MHz
        set_timings_below_100MHz_operation
+       b       common_to_lower_equal_100MHz
+
+set_timmings_100MHz:
+       restore_mmdc_settings_info
+       set_mmdc_misc_ralat_2_cycles
+
+common_to_lower_equal_100MHz:
        /*
         * Prior to reducing the DDR frequency (at 528/400 MHz),
         * read the Measure unit count bits (MU_UNIT_DEL_NUM)