MLK-14279 arm: imx: remove PTC1 control on i.MX7ULP during VLLS

On A2 board, NVCC_DRAM_SW power control is changed from PTC1
to PTB6, and PTB6 will be controlled by M4, so A7 does NOT
need to control this pin during VLLS, M4 will do it.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

diff --git a/arch/arm/mach-imx/suspend-imx7ulp.S b/arch/arm/mach-imx/suspend-imx7ulp.S
index bb250c6..f98c965 100644 (file)
--- a/arch/arm/mach-imx/suspend-imx7ulp.S
+++ b/arch/arm/mach-imx/suspend-imx7ulp.S
@@ -321,15 +321,6 @@ poll_dvfs_set:
        ands    r7, r7, #(1 << 24)
        beq     poll_dvfs_set
 
-       /* turn off NVCC_DRAM_SW - PTC1 */
-       ldr     r10, [r0, #PM_INFO_PM_INFO_GPIOC_VBASE_OFFSET]
-       ldr     r7, [r10, #GPIO_PDDR]
-       orr     r7, #(1 << 1)
-       str     r7, [r10, #GPIO_PDDR]
-       ldr     r7, [r10, #GPIO_PDOR]
-       orr     r7, #(1 << 1)
-       str     r7, [r10, #GPIO_PDOR]
-
        /* switch NIC clock to FIRC */
        ldr     r10, [r0, #PM_INFO_PM_INFO_SCG1_VBASE_OFFSET]
        ldr     r7, [r10, #SCG_NICCCR]
@@ -375,18 +366,6 @@ poll_dvfs_set:
        nop
        nop
 
-       /* turn on NVCC_DRAM_SW - PTC1 */
-       ldr     r10, [r0, #PM_INFO_PM_INFO_GPIOC_VBASE_OFFSET]
-       ldr     r7, [r10, #GPIO_PDOR]
-       bic     r7, #(1 << 1)
-       str     r7, [r10, #GPIO_PDOR]
-
-       /* gpioc needs 400us to ramp up, here use ~800us */
-       ldr     r7, =50000
-wait_gpio_up_vlps:
-       subs    r7, #0x1
-       bne     wait_gpio_up_vlps
-
        /* clear core0's entry and parameter */
        ldr     r10, [r0, #PM_INFO_PM_INFO_SIM_VBASE_OFFSET]
        mov     r7, #0x0
@@ -556,26 +535,6 @@ resume:
        orr     r7, r7, #(1 << 30)
        str     r7, [r11, #0x3c]
 
-       /* enable PTC1 IOMUXC */
-       ldr     r11, =MX7ULP_IOMUXC1_BASE_ADDR
-       ldr     r7, =0x20100
-       str     r7, [r11, #0x4]
-
-       /* output PTC1 to 0 */
-       ldr     r11, =MX7ULP_GPIOC_BASE_ADDR
-       ldr     r7, [r11, #GPIO_PDDR]
-       orr     r7, #(1 << 1)
-       str     r7, [r11, #GPIO_PDDR]
-       ldr     r7, [r11, #GPIO_PDOR]
-       bic     r7, #(1 << 1)
-       str     r7, [r11, #GPIO_PDOR]
-
-       /* gpioc needs 400us to ramp up, here use ~800us */
-       ldr     r7, =50000
-wait_gpio_up_vlls:
-       subs    r7, #0x1
-       bne     wait_gpio_up_vlls
-
        restore_mmdc_settings
        mov     pc, lr
 ENDPROC(imx7ulp_suspend)