add usdhc1/usdhc2/usdhc3 support for IOMMU
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
power-domains = <&pd_conn_sdch0>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
+ iommus = <&smmu 0x11 0x7f80>;
status = "disabled";
};
power-domains = <&pd_conn_sdch1>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
+ iommus = <&smmu 0x11 0x7f80>;
status = "disabled";
};
assigned-clocks = <&clk IMX8QM_SDHC2_DIV>;
assigned-clock-rates = <200000000>;
power-domains = <&pd_conn_sdch2>;
+ iommus = <&smmu 0x11 0x7f80>;
status = "disabled";
};