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CPU Architecture version
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+Power10 Power ISA v3.1
Power9 Power ISA v3.0B
Power8 Power ISA v2.07
Power7 Power ISA v2.06
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CPU VMX (aka. Altivec)
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+Power10 Yes
Power9 Yes
Power8 Yes
Power7 Yes
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CPU VSX
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+Power10 Yes
Power9 Yes
Power8 Yes
Power7 Yes
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CPU Transactional Memory
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+Power10 No (* see Power ISA v3.1, "Appendix A. Notes on the Removal of Transactional Memory from the Architecture")
Power9 Yes (* see transactional_memory.txt)
Power8 Yes
Power7 No