Add i.MX8QXP DDR3L validation board support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-ov5640.dtb \
imx8qxp-mek-enet2.dtb imx8qxp-mek-enet2-tja1100.dtb imx8qxp-mek-sof.dtb \
imx8qxp-mek-rpmsg.dtb imx8qxp-mek-a0.dtb imx8qxp-lpddr4-val-a0.dtb \
- imx8qxp-lpddr4-val.dtb imx8qxp-lpddr4-val-mqs.dtb \
+ imx8qxp-lpddr4-val.dtb imx8qxp-lpddr4-val-mqs.dtb imx8qxp-ddr3l-val.dtb \
imx8qxp-lpddr4-val-spdif.dtb
dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8qxp-lpddr4-val.dts"
+
+/ {
+ model = "Freescale i.MX8QXP DDR3L VALIDATION";
+ compatible = "fsl,imx8qxp-ddr3l-val", "fsl,imx8qxp";
+
+ reserved-memory {
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0 0x14000000>;
+ alloc-ranges = <0 0x96000000 0 0x14000000>;
+ linux,cma-default;
+ };
+ };
+};