MLK-13413 ARM: imx6sll-evk: add Murata Type ZP (BCM4339) module support

Add Murata Type ZP (BCM4339) module support on i.MX6SLL platforms:
- i.MX6SLL EVK (SD3 slot + BT connector) + Murata adapter V2.0

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5d0f808..e3a1157 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -523,7 +523,8 @@ dtb-$(CONFIG_SOC_IMX6SLL) += \
        imx6sll-lpddr3-arm2-csi.dtb \
        imx6sll-lpddr3-arm2-ecspi.dtb \
        imx6sll-lpddr3-arm2-spdif.dtb \
-       imx6sll-evk.dtb
+       imx6sll-evk.dtb \
+       imx6sll-evk-btwifi.dtb
 dtb-$(CONFIG_SOC_IMX7D) += \
        imx7d-cl-som-imx7.dtb \
        imx7d-colibri-eval-v3.dtb \

diff --git a/arch/arm/boot/dts/imx6sll-evk-btwifi.dts b/arch/arm/boot/dts/imx6sll-evk-btwifi.dts
new file mode 100644 (file)
index 0000000..431498f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sll-evk-btwifi.dts
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * NOTE: This DTS file is written for plugging in Murata Wi-Fi/BT EVK into Slot
+ * SD1 and using Murata i.MX InterConnect Ver 2.0 Adapter. Bluetooth UART &
+ * control signals are connected via ribbon cable (J1701 connector).
+ */
+
+#include "imx6sll-evk.dts"
+
+/ {
+       regulators {
+               wlreg_on: fixedregulator@100 {
+                       compatible = "regulator-fixed";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       regulator-name = "wlreg_on";
+                       gpio = <&gpio3 24 0>;
+                       startup-delay-us = <100>;
+                       enable-active-high;
+               };
+       };
+
+       bcmdhd_wlan_0: bcmdhd_wlan@0 {
+               compatible = "android,bcmdhd_wlan";
+               wlreg_on-supply = <&wlreg_on>;
+       };
+};
+
+&iomuxc {
+       imx6ul-evk-murata-v2 {
+               pinctrl_wifi: wifigrp {
+                       fsl,pins = <
+                               MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0x17059 /* WL_REG_ON */
+                               MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0x17059 /* WL_HOST_WAKE */
+                       >;
+               };
+       };
+};
+
+&lcdif {
+       status = "disabled";
+};
+
+&reg_sd3_vmmc {
+       regulator-always-on;
+};
+
+&uart5 {
+       status = "okay";
+};
+
+&usdhc3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc3_100mhz &pinctrl_wifi>;
+       no-1-8-v;
+       non-removable;
+       cd-post;
+       pm-ignore-notify;
+       wifi-host; /* add hook for SD card detect mechanism for BCMDHD driver */
+};

diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts
index 78d37f7..4b4e339 100644 (file)
--- a/arch/arm/boot/dts/imx6sll-evk.dts
+++ b/arch/arm/boot/dts/imx6sll-evk.dts
@@ -492,6 +492,25 @@
                        >;
                };
 
+               pinctrl_uart5: uart5grp {
+                       fsl,pins = <
+                               MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x1b0b1  /* bt reg on */
+                               MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x1b0b1
+                               MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x1b0b1
+                               MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x1b0b1
+                               MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x1b0b1
+                       >;
+               };
+
+               pinctrl_uart5dte: uart5dtegrp {
+                       fsl,pins = <
+                               MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x1b0b1
+                               MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x1b0b1
+                               MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x1b0b1
+                               MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x1b0b1
+                       >;
+               };
+
                pinctrl_usdhc1: usdhc1grp {
                        fsl,pins = <
                                MX6SLL_PAD_SD1_CMD__SD1_CMD     0x17059
@@ -650,6 +669,16 @@
        status = "okay";
 };
 
+&uart5 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart5>;
+       fsl,uart-has-rtscts;
+       /* for DTE mode, add below change */
+       /* fsl,dte-mode; */
+       /* pinctrl-0 = <&pinctrl_uart5dte>; */
+       status = "disabled";
+};
+
 &usdhc1 {
        pinctrl-names = "default", "state_100mhz", "state_200mhz";
        pinctrl-0 = <&pinctrl_usdhc1>;

diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index 45e38b0..7435372 100644 (file)
--- a/arch/arm/boot/dts/imx6sll.dtsi
+++ b/arch/arm/boot/dts/imx6sll.dtsi
@@ -28,9 +28,9 @@
                mmc2 = &usdhc3;
                serial0 = &uart1;
                serial1 = &uart2;
-               serial3 = &uart3;
-               serial4 = &uart4;
-               serial5 = &uart5;
+               serial2 = &uart3;
+               serial3 = &uart4;
+               serial4 = &uart5;
                spi0 = &ecspi1;
                spi1 = &ecspi2;
                spi3 = &ecspi3;
@@ -263,7 +263,7 @@
                                };
 
                                uart4: serial@02018000 {
-                                       compatible = "fsl,imx6sll-uart", "fsl-imx21-uart";
+                                       compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl-imx21-uart";
                                        reg = <0x02018000 0x4000>;
                                        interrupts =<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                                        dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
@@ -287,7 +287,7 @@
                                };
 
                                uart2: serial@02024000 {
-                                       compatible = "fsl,imx6sll-uart", "fsl,imx21-uart";
+                                       compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl-imx21-uart";
                                        reg = <0x02024000 0x4000>;
                                        interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
                                        dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
@@ -338,7 +338,7 @@
                                };
 
                                uart3: serial@02034000 {
-                                       compatible = "fsl,imx6sll-uart", "fsl,imx21-uart";
+                                       compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl-imx21-uart";
                                        reg = <0x02034000 0x4000>;
                                        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
                                        dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
@@ -520,6 +520,7 @@
                                fsl,tempmon = <&anatop>;
                                fsl,tempmon-data = <&ocotp>;
                                clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
+                               status = "disabled";
                        };
 
                        usbphy1: usbphy@020c9000 {
@@ -834,7 +835,7 @@
                        };
 
                        uart5: serial@021f4000 {
-                               compatible = "fsl,imx6sll-uart", "fsl-imx21-uart";
+                               compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl-imx21-uart";
                                reg = <0x021f4000 0x4000>;
                                interrupts =<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
                                dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;