MLK-15002 mmc: sdhci-esdhc-imx: fix HS400 timing issue

commit 3f0191b80cf1 ("MLK-14381 mmc: sdhci-esdhc-imx: reset tuning
circuit when system resume") add tuning reset when the timing is
MMC_TIMING_LEGACY/MMC_TIMING_MMC_HS/MMC_TIMING_SD_HS. For timing
MMC_TIMING_MMC_HS, we can not do tuning reset, otherwise HS400
timing is not right.

Here is the process of config HS400, it do tuning in HS200 mode,
then switch to HS mode and 8 bit DDR mode, finally switch to HS400
mode. If we do tuning reset in HS mode, this will cause HS400 mode
lost the tuning setting, which will cause CRC error.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 6996721..df5efd3 100644 (file)
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -993,6 +993,8 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
        case MMC_TIMING_UHS_SDR25:
        case MMC_TIMING_UHS_SDR50:
        case MMC_TIMING_UHS_SDR104:
+       case MMC_TIMING_SD_HS:
+       case MMC_TIMING_MMC_HS:
        case MMC_TIMING_MMC_HS200:
                writel(m, host->ioaddr + ESDHC_MIX_CTRL);
                break;
@@ -1020,7 +1022,6 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
                esdhc_set_strobe_dll(host);
                break;
        case MMC_TIMING_LEGACY:
-       default:
                esdhc_reset_tuning(host);
                break;
        }