MLK-17319-2 arm64: dts: add emvsim0 device node for imx8qm-mek

add emvsim0 device node for imx8qm-mek to support EMVSIM

Signed-off-by: Gao Pan <pandy.gao@nxp.com>
Reviewed-by: Andy Duan <fugang.duan@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
index 9cb0702..05a21e3 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
@@ -418,6 +418,16 @@
                        >;
                };
 
+               pinctrl_sim0: sim0grp {
+                       fsl,pins = <
+                               SC_P_SIM0_CLK_DMA_SIM0_CLK              0x21
+                               SC_P_SIM0_IO_DMA_SIM0_IO                0x21
+                               SC_P_SIM0_PD_DMA_SIM0_PD                0x21
+                               SC_P_SIM0_POWER_EN_DMA_SIM0_POWER_EN    0x21
+                               SC_P_SIM0_RST_DMA_SIM0_RST              0x21
+                       >;
+               };
+
                pinctrl_typec: typecgrp {
                        fsl,pins = <
                                SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19       0x60
@@ -607,6 +617,12 @@
        status = "okay";
 };
 
+&emvsim0 {
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&pinctrl_sim0>;
+       pinctrl-1 = <&pinctrl_sim0>;
+       status = "okay";
+};
 &sai1 {
        assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>,
                        <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
index d13991f..ddcdeb1 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
@@ -825,8 +825,16 @@
                        };
                        pd_dma_emvsim0: PD_DMA_EMVSIM_0 {
                                reg = <SC_R_EMVSIM_0>;
-                               #power-domain-cells = <0>;
                                power-domains = <&pd_dma>;
+                               #power-domain-cells = <0>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               pd_ldo1_sim: LDO1_SIM {
+                                       reg = <SC_R_BOARD_R2>;
+                                       #power-domain-cells = <0>;
+                                       power-domains = <&pd_dma_emvsim0>;
+                               };
                        };
                        pd_dma_emvsim1: PD_DMA_EMVSIM_1 {
                                reg = <SC_R_EMVSIM_1>;
@@ -1408,6 +1416,17 @@
                };
        };
 
+       emvsim0: sim0@5a0d0000 {
+               compatible = "fsl,imx8-emvsim";
+               reg = <0x0 0x5a0d0000 0x0 0x10000>;
+               interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clk IMX8QM_EMVSIM0_CLK>,
+                        <&clk IMX8QM_EMVSIM0_IPG_CLK>;
+               clock-names = "sim", "ipg";
+               power-domains = <&pd_ldo1_sim>;
+               status = "disabled";
+       };
+
        hdmi:hdmi@56268000 {
                #address-cells = <1>;
                #size-cells = <0>;