MLK-21834-2 imx8qxp_mek: Update board codes and config

Add ENET no-DM support, CDNS USB3 host/gadget, M4 bootaux and memtest etc
Update some SPL configs:
1. Remove FIT support and enable TINY printf for saving SPL size.
2. Fix wrong SPL regulator driver enabled, show use fixed regulator not
   gpio.
3. Add flexspi defconfig which uses SPI relevant SPL configs and disable
   MMC, GPIO and regulator SPL drivers.
4. Enable the panic. Since we use PSCI to reset, but ATF is not boot when
   SPL is running.
5. Use full malloc not simple malloc which has dedicated malloc pool
   to support large pool size. The simple malloc size is also used by
   early malloc which occupies the stack space. This causes we can't
   have a large malloc pool

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit db8230514ced8e6411c6d4a9089c5223cdf640ef)

diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index e866b46..162c2bc 100644 (file)
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -28,6 +28,7 @@
 #include <asm/setup.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <spl.h>
+#include <env.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
index d79312a..0b33b1e 100644 (file)
--- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c
+++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
@@ -21,9 +21,17 @@
 #include <asm/arch/snvs_security_sc.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/sys_proto.h>
+#include <usb.h>
+#include "../common/tcpc.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define ENET_INPUT_PAD_CTRL    ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+                                               | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_NORMAL_PAD_CTRL   ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+                                               | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
 #define GPIO_PAD_CTRL  ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
                         (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
                         (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
@@ -85,20 +93,123 @@ static inline void board_gpio_init(void) {}
 #if IS_ENABLED(CONFIG_FEC_MXC)
 #include <miiphy.h>
 
+#ifndef CONFIG_DM_ETH
+static iomux_cfg_t pad_enet1[] = {
+       SC_P_SPDIF0_TX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+       SC_P_SPDIF0_RX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+       SC_P_ESAI0_TX3_RX2 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+       SC_P_ESAI0_TX2_RX3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+       SC_P_ESAI0_TX1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+       SC_P_ESAI0_TX0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+       SC_P_ESAI0_SCKR | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+       SC_P_ESAI0_TX4_RX1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+       SC_P_ESAI0_TX5_RX0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+       SC_P_ESAI0_FST  | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+       SC_P_ESAI0_SCKT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+       SC_P_ESAI0_FSR  | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+
+       /* Shared MDIO */
+       SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+       SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+};
+
+static iomux_cfg_t pad_enet0[] = {
+       SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+       SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+       SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+       SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+       SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+       SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+       SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+       SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+       SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+       SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+       SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+       SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+
+       /* Shared MDIO */
+       SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+       SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+       if (0 == CONFIG_FEC_ENET_DEV)
+               imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0));
+       else
+               imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1));
+}
+
+static void enet_device_phy_reset(void)
+{
+       struct gpio_desc desc;
+       int ret;
+
+       /* The BB_PER_RST_B will reset the ENET1 PHY */
+       if (0 == CONFIG_FEC_ENET_DEV) {
+               ret = dm_gpio_lookup_name("gpio@1a_4", &desc);
+               if (ret)
+                       return;
+
+               ret = dm_gpio_request(&desc, "enet0_reset");
+               if (ret)
+                       return;
+
+               dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+               dm_gpio_set_value(&desc, 0);
+               udelay(50);
+               dm_gpio_set_value(&desc, 1);
+       }
+
+       /* The board has a long delay for this reset to become stable */
+       mdelay(200);
+}
+
+int board_eth_init(bd_t *bis)
+{
+       int ret;
+       struct power_domain pd;
+
+       printf("[%s] %d\n", __func__, __LINE__);
+
+       /* Reset ENET PHY */
+       enet_device_phy_reset();
+
+       if (CONFIG_FEC_ENET_DEV) {
+               if (!power_domain_lookup_name("conn_enet1", &pd))
+                       power_domain_on(&pd);
+       } else {
+               if (!power_domain_lookup_name("conn_enet0", &pd))
+                       power_domain_on(&pd);
+       }
+
+       setup_iomux_fec();
+
+       ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
+               CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+       if (ret)
+               printf("FEC1 MXC: %s:failed\n", __func__);
+
+       return ret;
+}
+
 int board_phy_config(struct phy_device *phydev)
 {
+       if (phydev->drv->config)
+               phydev->drv->config(phydev);
+
        phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
        phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
 
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
        phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
        phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
 
-       if (phydev->drv->config)
-               phydev->drv->config(phydev);
-
        return 0;
 }
 #endif
+#endif
 
 int checkboard(void)
 {
@@ -110,10 +221,115 @@ int checkboard(void)
        return 0;
 }
 
+#ifdef CONFIG_USB
+
+#ifdef CONFIG_USB_TCPC
+struct gpio_desc type_sel_desc;
+static iomux_cfg_t ss_mux_gpio[] = {
+       SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+struct tcpc_port port;
+struct tcpc_port_config port_config = {
+       .i2c_bus = 1,
+       .addr = 0x50,
+       .port_type = TYPEC_PORT_DFP,
+};
+
+void ss_mux_select(enum typec_cc_polarity pol)
+{
+       if (pol == TYPEC_POLARITY_CC1)
+               dm_gpio_set_value(&type_sel_desc, 0);
+       else
+               dm_gpio_set_value(&type_sel_desc, 1);
+}
+
+static void setup_typec(void)
+{
+       int ret;
+       struct gpio_desc typec_en_desc;
+
+       imx8_iomux_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
+       ret = dm_gpio_lookup_name("GPIO5_9", &type_sel_desc);
+       if (ret) {
+               printf("%s lookup GPIO5_9 failed ret = %d\n", __func__, ret);
+               return;
+       }
+
+       ret = dm_gpio_request(&type_sel_desc, "typec_sel");
+       if (ret) {
+               printf("%s request typec_sel failed ret = %d\n", __func__, ret);
+               return;
+       }
+
+       dm_gpio_set_dir_flags(&type_sel_desc, GPIOD_IS_OUT);
+
+       ret = dm_gpio_lookup_name("gpio@1a_7", &typec_en_desc);
+       if (ret) {
+               printf("%s lookup gpio@1a_7 failed ret = %d\n", __func__, ret);
+               return;
+       }
+
+       ret = dm_gpio_request(&typec_en_desc, "typec_en");
+       if (ret) {
+               printf("%s request typec_en failed ret = %d\n", __func__, ret);
+               return;
+       }
+
+       /* Enable SS MUX */
+       dm_gpio_set_dir_flags(&typec_en_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+       tcpc_init(&port, port_config, &ss_mux_select);
+}
+#endif
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+       int ret = 0;
+
+       if (index == 1) {
+               if (init == USB_INIT_HOST) {
+#ifdef CONFIG_USB_TCPC
+                       ret = tcpc_setup_dfp_mode(&port);
+#endif
+#ifdef CONFIG_USB_CDNS3_GADGET
+               } else {
+#ifdef CONFIG_USB_TCPC
+                       ret = tcpc_setup_ufp_mode(&port);
+                       printf("%d setufp mode %d\n", index, ret);
+#endif
+#endif
+               }
+       }
+
+       return ret;
+
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+       int ret = 0;
+
+       if (index == 1) {
+               if (init == USB_INIT_HOST) {
+#ifdef CONFIG_USB_TCPC
+                       ret = tcpc_disable_src_vbus(&port);
+#endif
+               }
+       }
+
+       return ret;
+}
+#endif
+
 int board_init(void)
 {
        board_gpio_init();
 
+#if defined(CONFIG_USB) && defined(CONFIG_USB_TCPC)
+       setup_typec();
+#endif
+
 #ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO
        {
                int ret = snvs_security_sc_init();

diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c
index ae6b64f..5734545 100644 (file)
--- a/board/freescale/imx8qxp_mek/spl.c
+++ b/board/freescale/imx8qxp_mek/spl.c
@@ -77,9 +77,6 @@ int board_fit_config_name_match(const char *name)
 
 void board_init_f(ulong dummy)
 {
-       /* Clear global data */
-       memset((void *)gd, 0, sizeof(gd_t));
-
        /* Clear the BSS. */
        memset(__bss_start, 0, __bss_end - __bss_start);
 

diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index e60eb80..1f12d10 100644 (file)
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -1,12 +1,14 @@
 CONFIG_ARM=y
 CONFIG_ARCH_IMX8=y
 CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
-CONFIG_NR_DRAM_BANKS=3
-CONFIG_ENV_SIZE=0x1000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_TEXT_BASE=0x100000
@@ -14,17 +16,23 @@ CONFIG_SPL_LOAD_IMX_CONTAINER=y
 CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
 CONFIG_TARGET_IMX8QXP_MEK=y
 CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
+CONFIG_SPL_ENV_IS_NOWHERE=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg"
 CONFIG_BOOTDELAY=3
 CONFIG_LOG=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_POWER_DOMAIN=y
@@ -36,7 +44,6 @@ CONFIG_CMD_CPU=y
 # CONFIG_CMD_CRC32 is not set
 CONFIG_CMD_CLK=y
 CONFIG_CMD_DM=y
-CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -65,6 +72,10 @@ CONFIG_MISC=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ADDR_ENABLE=y
 CONFIG_PHY_ATHEROS=y
@@ -83,10 +94,46 @@ CONFIG_DM_REGULATOR=y
 CONFIG_SPL_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_SCU_THERMAL=y
 CONFIG_SPL_TINY_MEMSET=y
 # CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_SMC_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
\ No newline at end of file

diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h
index 49548dd..bc3393e 100644 (file)
--- a/include/configs/imx8qxp_mek.h
+++ b/include/configs/imx8qxp_mek.h
@@ -13,25 +13,24 @@
 #include "imx_env.h"
 
 #ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_MAX_SIZE                            (124 * 1024)
+#define CONFIG_SPL_MAX_SIZE                            (192 * 1024)
 #define CONFIG_SYS_MONITOR_LEN                         (1024 * 1024)
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR                0x800
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR                0x1040 /* (32K + 2Mb)/sector_size */
 
 #define CONFIG_SPL_LDSCRIPT            "arch/arm/cpu/armv8/u-boot-spl.lds"
-#define CONFIG_SPL_STACK               0x013E000
-#define CONFIG_SPL_BSS_START_ADDR      0x00128000
+#define CONFIG_SPL_STACK               0x013fff0
+#define CONFIG_SPL_BSS_START_ADDR      0x00130000
 #define CONFIG_SPL_BSS_MAX_SIZE                0x1000  /* 4 KB */
-#define CONFIG_SYS_SPL_MALLOC_START    0x00120000
-#define CONFIG_SYS_SPL_MALLOC_SIZE     0x3000  /* 12 KB */
+#define CONFIG_SYS_SPL_MALLOC_START    0x82200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x80000 /* 512 KB */
 #define CONFIG_SERIAL_LPUART_BASE      0x5a060000
-#define CONFIG_MALLOC_F_ADDR           0x00120000
+#define CONFIG_MALLOC_F_ADDR           0x00138000
 
 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
 
 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
 
-#define CONFIG_OF_EMBED
 #endif
 
 #define CONFIG_REMAKE_ELF
@@ -53,6 +52,12 @@
 #define AHAB_ENV "sec_boot=no\0"
 #endif
 
+/* Boot M4 */
+#define M4_BOOT_ENV \
+       "m4_0_image=m4_0.bin\0" \
+       "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
+       "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
+
 #define CONFIG_MFG_ENV_SETTINGS \
        CONFIG_MFG_ENV_SETTINGS_DEFAULT \
        "initrd_addr=0x83100000\0" \
@@ -63,6 +68,7 @@
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS              \
        CONFIG_MFG_ENV_SETTINGS \
+       M4_BOOT_ENV \
        AHAB_ENV \
        "script=boot.scr\0" \
        "image=Image\0" \
@@ -76,7 +82,7 @@
        "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
        "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
        "mmcautodetect=yes\0" \
-       "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot}\0 " \
+       "mmcargs=setenv bootargs console=${console},${baudrate} earlycon root=${mmcroot}\0 " \
        "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
        "bootscript=echo Running bootscript from mmc ...; " \
                "source\0" \
@@ -104,7 +110,7 @@
                                "echo wait for boot; " \
                        "fi;" \
                "fi;\0" \
-       "netargs=setenv bootargs console=${console},${baudrate} " \
+       "netargs=setenv bootargs console=${console},${baudrate} earlycon " \
                "root=/dev/nfs " \
                "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
        "netboot=echo Booting from net ...; " \
@@ -160,7 +166,13 @@
 
 #define CONFIG_SYS_INIT_SP_ADDR         0x80200000
 
-/* Default environment is in SD */
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_ENV_SECT_SIZE   (128 * 1024)
+#define CONFIG_ENV_SPI_BUS     CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS      CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE    CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ  CONFIG_SF_DEFAULT_SPEED
+#endif
 
 #define CONFIG_SYS_MMC_IMG_LOAD_PART   1
 
@@ -178,6 +190,17 @@
 /* LPDDR4 board total DDR is 3GB */
 #define PHYS_SDRAM_2_SIZE              0x40000000      /* 1 GB */
 
+/* Serial */
+#define CONFIG_BAUDRATE                        115200
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_CBSIZE              2048
+#define CONFIG_SYS_MAXARGS             64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
+                                       sizeof(CONFIG_SYS_PROMPT) + 16)
+
 /* Generic Timer Definitions */
 #define COUNTER_FREQUENCY              8000000 /* 8MHz */
 
@@ -185,12 +208,43 @@
 #define CONFIG_PCA953X
 #endif
 
+#define CONFIG_SERIAL_TAG
+
+/* USB Config */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USBD_HS
+
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+
+#endif
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+/* USB OTG controller configs */
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC          (PORT_PTS_UTMI | PORT_PTS_PTW)
+#endif
+
 /* Networking */
+#define CONFIG_FEC_ENET_DEV 0
+
+#if (CONFIG_FEC_ENET_DEV == 0)
+#define IMX_FEC_BASE                   0x5B040000
+#define CONFIG_FEC_MXC_PHYADDR          0x0
+#define CONFIG_ETHPRIME                 "eth0"
+#elif (CONFIG_FEC_ENET_DEV == 1)
+#define IMX_FEC_BASE                   0x5B050000
+#define CONFIG_FEC_MXC_PHYADDR          0x1
+#define CONFIG_ETHPRIME                 "eth1"
+#endif
+
 #define CONFIG_FEC_XCV_TYPE            RGMII
 
-/* Misc configuration */
-#define CONFIG_SYS_CBSIZE      2048
-#define CONFIG_SYS_MAXARGS     64
-#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE
 
 #endif /* __IMX8QXP_MEK_H */