MXSCM-241-2 arm: imx: coherency issues after updating lpddr2 busfreq

After a frequency transition, like 400MHz to 24Mhz, on i.mx6DQ SCM
systems (which use lpddr2), the curr_ddr_rate variable retains its
previous cached value causing the next frequency update transition
to fail by following a wrong flow which results in a complete hang
of the system.

Issuing an L1 cache flush during the freq update routine (as in in
MXSCM-241-1) and moving up the curr_ddr_rate variable before calling
tge freq update alleviates the problem.

Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>

diff --git a/arch/arm/mach-imx/busfreq_lpddr2.c b/arch/arm/mach-imx/busfreq_lpddr2.c
index dc8a311..7dca4ba 100644 (file)
--- a/arch/arm/mach-imx/busfreq_lpddr2.c
+++ b/arch/arm/mach-imx/busfreq_lpddr2.c
@@ -254,13 +254,13 @@ int update_lpddr2_freq_smp(int ddr_rate)
         */
        ttbr1 = save_ttbr1();
 
+       curr_ddr_rate = ddr_rate;
+
        /* Now change DDR frequency. */
        mx6_change_lpddr2_freq_smp(ddr_rate, mmdc_settings_info);
 
        restore_ttbr1(ttbr1);
 
-       curr_ddr_rate = ddr_rate;
-
 #ifdef CONFIG_SMP
        wmb();
        /* DDR frequency change is done . */