drm/amdgpu/gfx10: add placeholder for navi14 golden settings

To be filled in once available.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d61d70e..0741ae3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -116,6 +116,11 @@ static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
        /* Pending on emulation bring up */
 };
 
+static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
+{
+       /* Pending on emulation bring up */
+};
+
 #define DEFAULT_SH_MEM_CONFIG \
        ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
         (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
@@ -257,6 +262,14 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
                                                golden_settings_gc_10_0_nv10,
                                                (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
                break;
+       case CHIP_NAVI14:
+               soc15_program_register_sequence(adev,
+                                               golden_settings_gc_10_1,
+                                               (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
+               soc15_program_register_sequence(adev,
+                                               golden_settings_gc_10_1_nv14,
+                                               (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
+               break;
        default:
                break;
        }