MLK-13362-2 ARM: imx: fix audio bus mode hang for imx6dq lpddr2

The double MU count operations should be only done when changing the
MMDC frequency from 400MHz to a low frequency(100MHz or 24MHz).
Otherwise, the MU count may overflow and lead to system hang/panic issue.

This is basically a porting of 4d09bf110b878a6f720ee9d19c8b64ceace95fbe
to imx6dq lppdr2.

Also a member "freq" has been added to the mmdc_settings_info structure
to store the current ddr frequency on iram settings to be able to execute
the double MU count, only on 400MHz mode and bypass the operation
otherwise within the update freq routine.

Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>

diff --git a/arch/arm/mach-imx/busfreq_lpddr2.c b/arch/arm/mach-imx/busfreq_lpddr2.c
index 7dca4ba..2ef1806 100644 (file)
--- a/arch/arm/mach-imx/busfreq_lpddr2.c
+++ b/arch/arm/mach-imx/busfreq_lpddr2.c
@@ -71,6 +71,7 @@ extern unsigned long iram_tlb_phys_addr;
 struct mmdc_settings_info {
        u32 size;
        void *settings;
+       int freq;
 } __aligned(8);
 static struct mmdc_settings_info *mmdc_settings_info;
 void (*mx6_change_lpddr2_freq_smp)(u32 ddr_freq, struct mmdc_settings_info
@@ -201,6 +202,7 @@ int update_lpddr2_freq_smp(int ddr_rate)
 
        mmdc_settings_info->size = mmdc_settings_size;
        mmdc_settings_info->settings = iram_mmdc_settings;
+       mmdc_settings_info->freq = curr_ddr_rate;
 
        /* ensure that all Cores are in WFE. */
        local_irq_disable();
@@ -351,7 +353,7 @@ int init_mmdc_lpddr2_settings_mx6q(struct platform_device *busfreq_pdev)
                        &wfe_smp_freq_change, wfe_code_size);
 #endif
        iram_settings_size = (void *)ddr_freq_change_iram_base + wfe_code_size + 0x8;
-       iram_mmdc_settings = (void *)iram_settings_size + 0x8;
+       iram_mmdc_settings = (void *)iram_settings_size + sizeof(*mmdc_settings_info);
        iram_ddr_freq_chage = (void *)iram_mmdc_settings + (mmdc_settings_size * 8) + 0x8;
        mmdc_settings_info = (struct mmdc_settings_info *)iram_settings_size;
 

diff --git a/arch/arm/mach-imx/lpddr2_freq_imx6q.S b/arch/arm/mach-imx/lpddr2_freq_imx6q.S
index 32e8ebd..6c9aac0 100644 (file)
--- a/arch/arm/mach-imx/lpddr2_freq_imx6q.S
+++ b/arch/arm/mach-imx/lpddr2_freq_imx6q.S
@@ -238,6 +238,13 @@ set_timmings_100MHz:
        set_mmdc_misc_ralat_2_cycles
 
 common_to_lower_equal_100MHz:
+
+       /* if MMDC is not in 400MHz mode, skip double mu count */
+       ldr     r5, [r1, #0x8]
+       ldr     r6, =400000000
+       cmp     r5, r6
+       bne     skip_lower_force_measure_ch1
+
        /*
         * Prior to reducing the DDR frequency (at 528/400 MHz),
         * read the Measure unit count bits (MU_UNIT_DEL_NUM)