MLK-16689: Add DDR PHY training flow for different frequency

On our i.MX8MQ EVK board, we will support three frequency point:
    1. 3200mts, DDRC core clock is 800MHz;
    2. 400mts, DDRC core clock is 100MHz;
    3. 100mts, DDRC core clock is 25MHz.

The 1D training flow need to be run once for each frequency. The
PHY training updated to support training different frequency point.

Additionally, the DDRC's registers of other frequency also need to
be configured.

Signed-off-by: Bai Ping <ping.bai@nxp.com>

diff --git a/board/freescale/imx8mq_evk/ddr/lpddr4_pub_train_0608_simple.c b/board/freescale/imx8mq_evk/ddr/lpddr4_pub_train_0608_simple.c
index 1786193..a3398e4 100644 (file)
--- a/board/freescale/imx8mq_evk/ddr/lpddr4_pub_train_0608_simple.c
+++ b/board/freescale/imx8mq_evk/ddr/lpddr4_pub_train_0608_simple.c
@@ -32,85 +32,47 @@ void lpddr4_800MHz_cfg_umctl2(void)
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000304, 0x00000001);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000030, 0x00000001);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000000, 0x83080020);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000000, 0x83080020);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000064, 0x006180e0);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000064, 0x006180e0);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000d0, 0xc003061B);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000d0, 0xc003061B);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000d4, 0x009D0000);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000d4, 0x009D0000);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000d8, 0x0000fe05);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000d8, 0x0000fe05);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000dc, 0x00d4002d);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000dc, 0x00d4002d);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000e0, 0x00310008);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000e0, 0x00310008);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000e4, 0x00040009);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000e4, 0x00040009);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000e8, 0x0046004d);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000e8, 0x0046004d);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000ec, 0x0005004d);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000ec, 0x0005004d);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000f4, 0x00000979);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000000f4, 0x00000979);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000100, 0x1a203522);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000100, 0x1a203522);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000104, 0x00060630);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000104, 0x00060630);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000108, 0x070e1214);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000108, 0x070e1214);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x0000010c, 0x00b0c006);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x0000010c, 0x00b0c006);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000110, 0x0f04080f);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000110, 0x0f04080f);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000114, 0x0d0d0c0c);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000114, 0x0d0d0c0c);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000118, 0x01010007);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000118, 0x01010007);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x0000011c, 0x0000060a);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x0000011c, 0x0000060a);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000120, 0x01010101);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000120, 0x01010101);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000124, 0x40000008);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000124, 0x40000008);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000128, 0x00050d01);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000128, 0x00050d01);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x0000012c, 0x01010008);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x0000012c, 0x01010008);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000130, 0x00020000);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000130, 0x00020000);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000134, 0x18100002);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000134, 0x18100002);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000138, 0x00000dc2);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000138, 0x00000dc2);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x0000013c, 0x80000000);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x0000013c, 0x80000000);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000144, 0x00a00050);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000144, 0x00a00050);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000180, 0x53200018);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000180, 0x53200018);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000184, 0x02800070);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000184, 0x02800070);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000188, 0x00000000);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000188, 0x00000000);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000190, 0x0397820a);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000190, 0x0397820a);
+       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00002190, 0x0397820a);
+       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00003190, 0x0397820a);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000194, 0x00020103);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000194, 0x00020103);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001a0, 0xe0400018);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001a0, 0xe0400018);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001a4, 0x00df00e4);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001a4, 0x00df00e4);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001a8, 0x00000000);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001a8, 0x00000000);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001b0, 0x00000011);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001b0, 0x00000011);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001b4, 0x0000170a);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001b4, 0x0000170a);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001c0, 0x00000001);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001c0, 0x00000001);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001c4, 0x00000000);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x000001c4, 0x00000000);
        /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
        dwc_ddrphy_apb_wr(DDRC_ADDRMAP0(0), 0x00000015);
        dwc_ddrphy_apb_wr(DDRC_ADDRMAP4(0), 0x00001F1F);
@@ -119,36 +81,58 @@ void lpddr4_800MHz_cfg_umctl2(void)
        dwc_ddrphy_apb_wr(DDRC_ADDRMAP5(0), 0x07070707);
        dwc_ddrphy_apb_wr(DDRC_ADDRMAP6(0), 0x08080707);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000240, 0x020f0c54);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000240, 0x020f0c54);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000244, 0x00000000);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000244, 0x00000000);
        dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000490, 0x00000001);
-       dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) +  0x00000490, 0x00000001);
-        /* performance setting */
-       dwc_ddrphy_apb_wr(DDRC_ODTCFG(0), 0x0b060908);
-       dwc_ddrphy_apb_wr(DDRC_ODTMAP(0), 0x00000000);
-       dwc_ddrphy_apb_wr(DDRC_SCHED(0), 0x29511505);
-       dwc_ddrphy_apb_wr(DDRC_SCHED1(0), 0x0000002c);
-       dwc_ddrphy_apb_wr(DDRC_PERFHPR1(0), 0x5900575b);
-       dwc_ddrphy_apb_wr(DDRC_PERFLPR1(0), 0x900093e7);
-       dwc_ddrphy_apb_wr(DDRC_PERFWR1(0), 0x02005574);
-       dwc_ddrphy_apb_wr(DDRC_DBG0(0), 0x00000016);
-       dwc_ddrphy_apb_wr(DDRC_DBG1(0), 0x00000000);
-       dwc_ddrphy_apb_wr(DDRC_DBGCMD(0), 0x00000000);
-       dwc_ddrphy_apb_wr(DDRC_SWCTL(0), 0x00000001);
-       dwc_ddrphy_apb_wr(DDRC_POISONCFG(0), 0x00000011);
-       dwc_ddrphy_apb_wr(DDRC_PCCFG(0), 0x00000111);
-       dwc_ddrphy_apb_wr(DDRC_PCFGR_0(0), 0x000010f3);
-       dwc_ddrphy_apb_wr(DDRC_PCFGW_0(0), 0x000072ff);
-       dwc_ddrphy_apb_wr(DDRC_PCTRL_0(0), 0x00000001);
-       dwc_ddrphy_apb_wr(DDRC_PCFGQOS0_0(0), 0x01110d00);
-       dwc_ddrphy_apb_wr(DDRC_PCFGQOS1_0(0), 0x00620790);
-       dwc_ddrphy_apb_wr(DDRC_PCFGWQOS0_0(0), 0x00100001);
-       dwc_ddrphy_apb_wr(DDRC_PCFGWQOS1_0(0), 0x0000041f);
-       dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEEN(0), 0x00000202);
-       dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEINT(0), 0xec78f4b5);
-       dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHCTL0(0), 0x00618040);
-       dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHTMG(0), 0x00610090);
+}
+
+void lpddr4_100MHz_cfg_umctl2(void)
+{
+       reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c);
+       reg32_write(DDRC_FREQ1_DRAMTMG1(0), 0x00030410);
+       reg32_write(DDRC_FREQ1_DRAMTMG2(0), 0x0305090c);
+       reg32_write(DDRC_FREQ1_DRAMTMG3(0), 0x00505006);
+       reg32_write(DDRC_FREQ1_DRAMTMG4(0), 0x05040305);
+       reg32_write(DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504);
+       reg32_write(DDRC_FREQ1_DRAMTMG6(0), 0x0a060004);
+       reg32_write(DDRC_FREQ1_DRAMTMG7(0), 0x0000090e);
+       reg32_write(DDRC_FREQ1_DRAMTMG14(0), 0x00000032);
+       reg32_write(DDRC_FREQ1_DRAMTMG15(0), 0x00000000);
+       reg32_write(DDRC_FREQ1_DRAMTMG17(0), 0x0036001b);
+       reg32_write(DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1);
+       reg32_write(DDRC_FREQ1_RFSHCTL0(0), 0x0020d040);
+       reg32_write(DDRC_FREQ1_DFITMG0(0), 0x03818200);
+       reg32_write(DDRC_FREQ1_ODTCFG(0), 0x0a1a096c);
+       reg32_write(DDRC_FREQ1_DFITMG2(0), 0x00000000);
+       reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x00038014);
+       reg32_write(DDRC_FREQ1_INIT3(0), 0x00840000);
+       reg32_write(DDRC_FREQ1_INIT6(0), 0x0000004d);
+       reg32_write(DDRC_FREQ1_INIT7(0), 0x0000004d);
+       reg32_write(DDRC_FREQ1_INIT4(0), 0x00310000);
+}
+
+void lpddr4_25MHz_cfg_umctl2(void)
+{
+       reg32_write(DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c);
+       reg32_write(DDRC_FREQ2_DRAMTMG1(0), 0x00030410);
+       reg32_write(DDRC_FREQ2_DRAMTMG2(0), 0x0305090c);
+       reg32_write(DDRC_FREQ2_DRAMTMG3(0), 0x00505006);
+       reg32_write(DDRC_FREQ2_DRAMTMG4(0), 0x05040305);
+       reg32_write(DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504);
+       reg32_write(DDRC_FREQ2_DRAMTMG6(0), 0x0a060004);
+       reg32_write(DDRC_FREQ2_DRAMTMG7(0), 0x0000090e);
+       reg32_write(DDRC_FREQ2_DRAMTMG14(0), 0x00000032);
+       reg32_write(DDRC_FREQ2_DRAMTMG15(0), 0x00000000);
+       reg32_write(DDRC_FREQ2_DRAMTMG17(0), 0x0036001b);
+       reg32_write(DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1);
+       reg32_write(DDRC_FREQ2_RFSHCTL0(0), 0x0020d040);
+       reg32_write(DDRC_FREQ2_DFITMG0(0), 0x03818200);
+       reg32_write(DDRC_FREQ2_ODTCFG(0), 0x0a1a096c);
+       reg32_write(DDRC_FREQ2_DFITMG2(0), 0x00000000);
+       reg32_write(DDRC_FREQ2_RFSHTMG(0), 0x0003800c);
+       reg32_write(DDRC_FREQ2_INIT3(0), 0x00840000);
+       reg32_write(DDRC_FREQ2_INIT6(0), 0x0000004d);
+       reg32_write(DDRC_FREQ2_INIT7(0), 0x0000004d);
+       reg32_write(DDRC_FREQ2_INIT4(0), 0x00310000);
 }
 
 void lpddr4_pub_train(void)
@@ -231,4 +215,16 @@ void lpddr4_pub_train(void)
        reg32_write(DDRC_PCTRL_0(0), 0x00000001);
        tmp = reg32_read(DDRC_CRCPARSTAT(0));
        reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
+
+       reg32_write(DDRC_SWCTL(0), 0x0);
+       lpddr4_100MHz_cfg_umctl2();
+       lpddr4_25MHz_cfg_umctl2();
+       reg32_write(DDRC_SWCTL(0), 0x1);
+
+       /* wait SWSTAT.sw_done_ack to 1 */
+       while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0)
+               ;
+
+       reg32_write(DDRC_SWCTL(0), 0x0);
+
 }

diff --git a/board/freescale/imx8mq_evk/ddr/train1d.c b/board/freescale/imx8mq_evk/ddr/train1d.c
index efda51b..60909f5 100644 (file)
--- a/board/freescale/imx8mq_evk/ddr/train1d.c
+++ b/board/freescale/imx8mq_evk/ddr/train1d.c
@@ -6,9 +6,62 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/ddr_memory_map.h>
 #include "lpddr4.h"
 
+void ddr_pll_bypass_100mts(void) {
+       /* change the clock source of dram_alt_clk_root to source 2 --100MHz */
+       reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(0),(0x7<<24)|(0x7<<16));
+       reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(0),(0x2<<24));
+
+       /* change the clock source of dram_apb_clk_root to source 2 --40MHz */
+       reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16));
+       reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x2<<24)|(0x1<<16));
+
+       /* disable the clock gating */
+       reg32_write(0x303A00EC,0x0000ffff); /* PGC_CPU_MAPPING */
+       reg32setbit(0x303A00F8,5);          /* PU_PGC_SW_PUP_REQ */
+
+       /* configure pll bypass mode */
+       reg32_write(0x30389804, 1<<24);
+
+       printf("PLL bypass to 100MTS setting done \n");
+}
+
+void ddr_pll_bypass_400mts(void) {
+    /* change the clock source of dram_alt_clk_root to source 2 --400MHz */
+    reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(0),(0x7<<24)|(0x7<<16));
+    reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(0),(0x5<<24));
+
+    /* change the clock source of dram_apb_clk_root to source 2 --40MHz/2 */
+    reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16));
+    reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x2<<24)|(0x1<<16));
+
+    /* disable the clock gating */
+    reg32_write(0x303A00EC,0x0000ffff); /* PGC_CPU_MAPPING */
+    reg32setbit(0x303A00F8,5);          /* PU_PGC_SW_PUP_REQ */
+
+    /* configure pll bypass mode */
+    reg32_write(0x30389804, 1<<24);
+
+    printf("PLL bypass to 400MTS setting done \n");
+}
+
+
+void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(int pstate)
+{
+       if (pstate == 2)
+               ddr_pll_bypass_100mts();
+       else if (pstate == 1)
+               ddr_pll_bypass_400mts();
+       else {
+               reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7 << 24) | (0x7 << 16));
+               reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x4 << 24) | (0x3 << 16));
+               reg32_write(0x30389808, 1 << 24);
+       }
+}
+
 void lpddr4_800M_cfg_phy(void) {
        unsigned int tmp, tmp_t;
 
@@ -26,6 +79,22 @@ void lpddr4_800M_cfg_phy(void) {
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1215f, 0x1ff);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1305f, 0x1ff);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1315f, 0x1ff);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11005f, 0x1ff);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11015f, 0x1ff);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11105f, 0x1ff);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11115f, 0x1ff);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11205f, 0x1ff);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11215f, 0x1ff);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11305f, 0x1ff);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11315f, 0x1ff);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21005f, 0x1ff);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21015f, 0x1ff);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21105f, 0x1ff);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21115f, 0x1ff);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21205f, 0x1ff);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21215f, 0x1ff);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21305f, 0x1ff);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21315f, 0x1ff);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x55, 0x1ff);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1055, 0x1ff);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2055, 0x1ff);
@@ -37,11 +106,23 @@ void lpddr4_800M_cfg_phy(void) {
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x8055, 0x1ff);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9055, 0x1ff);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200c5, 0x19);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200c5, 0x7);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200c5, 0x7);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2002e, 0x2);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002e, 0x2);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22002e, 0x2);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90204, 0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x190204, 0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x290204, 0x0);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20024, 0xab);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120024, 0xab);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220024, 0xab);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x0);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20056, 0x3);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120056, 0xa);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220056, 0xa);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1004d, 0xe00);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1014d, 0xe00);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1104d, 0xe00);
@@ -50,6 +131,22 @@ void lpddr4_800M_cfg_phy(void) {
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1214d, 0xe00);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1304d, 0xe00);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1314d, 0xe00);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11004d, 0xe00);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11014d, 0xe00);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11104d, 0xe00);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11114d, 0xe00);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11204d, 0xe00);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11214d, 0xe00);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11304d, 0xe00);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11314d, 0xe00);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21004d, 0xe00);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21014d, 0xe00);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21104d, 0xe00);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21114d, 0xe00);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21204d, 0xe00);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21214d, 0xe00);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21304d, 0xe00);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21314d, 0xe00);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10049, 0xe38);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10149, 0xe38);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11049, 0xe38);
@@ -58,6 +155,22 @@ void lpddr4_800M_cfg_phy(void) {
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12149, 0xe38);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13049, 0xe38);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13149, 0xe38);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110049, 0xe38);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110149, 0xe38);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111049, 0xe38);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111149, 0xe38);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112049, 0xe38);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112149, 0xe38);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113049, 0xe38);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113149, 0xe38);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210049, 0xe38);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210149, 0xe38);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211049, 0xe38);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211149, 0xe38);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212049, 0xe38);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212149, 0xe38);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213049, 0xe38);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213149, 0xe38);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x43, 0x21);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1043, 0x21);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2043, 0x21);
@@ -72,6 +185,8 @@ void lpddr4_800M_cfg_phy(void) {
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20075, 0x4);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20050, 0x0);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20008, 0x320);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120008, 0x64);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220008, 0x19);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20088, 0x9);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200b2, 0x19c);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10043, 0x5a1);
@@ -82,9 +197,31 @@ void lpddr4_800M_cfg_phy(void) {
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12143, 0x5a1);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13043, 0x5a1);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13143, 0x5a1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200b2, 0x19c);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110043, 0x5a1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110143, 0x5a1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111043, 0x5a1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111143, 0x5a1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112043, 0x5a1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112143, 0x5a1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113043, 0x5a1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113143, 0x5a1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200b2, 0x19c);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210043, 0x5a1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210143, 0x5a1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211043, 0x5a1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211143, 0x5a1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212043, 0x5a1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212143, 0x5a1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213043, 0x5a1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213143, 0x5a1);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200fa, 0x1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200fa, 0x1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200fa, 0x1);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20019, 0x1);
-       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f0, 0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120019, 0x1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220019, 0x1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f0, 0x660);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f1, 0x0);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f2, 0x4444);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f3, 0x8888);
@@ -96,13 +233,180 @@ void lpddr4_800M_cfg_phy(void) {
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000c, 0xc9);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000d, 0x7d1);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000e, 0x2c);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000b, 0xd);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000c, 0x1a);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000d, 0xfb);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000e, 0x10);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000b, 0x4);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000c, 0x7);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000d, 0x3f);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000e, 0x10);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20025, 0x0);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2002d, 0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002d, 0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22002d, 0x0);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20060, 0x2);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
        /* load the 1D training image */
        ddr4_load_train_code(FW_1D_IMAGE);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+       /* set the PHY input clock to the desired frequency for pstate 2 */
+       dwc_ddrphy_phyinit_userCustom_E_setDfiClk(2);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x102);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0x64);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x2828);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x14);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x121f);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x4);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d46);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x5);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x4);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d46);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x5);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0x400);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x3100);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x4600);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x500);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0x400);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x3100);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x4600);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, 0x4d);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, 0x500);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+extern void wait_ddrphy_training_complete(void);
+       wait_ddrphy_training_complete();
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+       /* set the PHY input clock to the desired frequency for pstate 1 */
+       dwc_ddrphy_phyinit_userCustom_E_setDfiClk(1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x101);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0x190);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x2828);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x14);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x121f);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x4);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d46);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x5);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x4);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d46);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x5);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031,0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0x400);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x3100);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x4600);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x500);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0x400);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x3100);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x4600);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x500);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+extern void wait_ddrphy_training_complete(void);
+       wait_ddrphy_training_complete();
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+       dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+       /* set the PHY input clock to the desired frequency for pstate 0 */
+       dwc_ddrphy_phyinit_userCustom_E_setDfiClk(0);
+
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0);
        dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0);