MLK-11457-03 ARM: dts: imx6sl-evk: add uart4 support

Add uart4 DCE and DTE pinctrl set. Since there have pin confliction,
so add new dts file. To avoid a flood of dts files, there comment out
DTE pinctrl set. If user want to test DTE mode, it needs to rebuild
the DTB file.

(cherry picked from commit a3602fa5796bb86ba432474220389ec712bde92a)

Signed-off-by: Fugang Duan <B38611@freescale.com>

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7543f45..c72c1be 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -412,6 +412,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
        imx6qp-sabresd.dtb
 dtb-$(CONFIG_SOC_IMX6SL) += \
        imx6sl-evk.dtb \
+       imx6sl-evk-uart.dtb \
        imx6sl-warp.dtb
 dtb-$(CONFIG_SOC_IMX6SX) += \
        imx6sx-nitrogen6sx.dtb \

diff --git a/arch/arm/boot/dts/imx6sl-evk-uart.dts b/arch/arm/boot/dts/imx6sl-evk-uart.dts
new file mode 100644 (file)
index 0000000..6179842
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-evk-uart.dts
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6sl-evk.dts"
+
+&uart4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart4_1>;
+       fsl,uart-has-rtscts;
+       status = "okay";
+       /* for DTE mode, add below change */
+       /* fsl,dte-mode; */
+       /* pinctrl-0 = <&pinctrl_uart4dte_1>; */
+};
+
+&usdhc1 {
+       status = "disabled";
+};

diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index 29de68b..33e6570 100644 (file)
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -409,6 +409,24 @@
                        >;
                };
 
+               pinctrl_uart4_1: uart4grp-1 {
+                       fsl,pins = <
+                               MX6SL_PAD_SD1_DAT4__UART4_RX_DATA       0x1b0b1
+                               MX6SL_PAD_SD1_DAT5__UART4_TX_DATA       0x1b0b1
+                               MX6SL_PAD_SD1_DAT7__UART4_CTS_B         0x1b0b1
+                               MX6SL_PAD_SD1_DAT6__UART4_RTS_B         0x1b0b1
+                       >;
+               };
+
+               pinctrl_uart4dte_1: uart4dtegrp-1 {
+                       fsl,pins = <
+                               MX6SL_PAD_SD1_DAT5__UART4_RX_DATA       0x1b0b1
+                               MX6SL_PAD_SD1_DAT4__UART4_TX_DATA       0x1b0b1
+                               MX6SL_PAD_SD1_DAT6__UART4_CTS_B         0x1b0b1
+                               MX6SL_PAD_SD1_DAT7__UART4_RTS_B         0x1b0b1
+                       >;
+               };
+
                pinctrl_usbotg1: usbotg1grp {
                        fsl,pins = <
                                MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID      0x17059