arm64: dts: imx8mm-somdevices.dtsi: Add SPI CAN controller.

Signed-off-by: Josep Orga <jorga@somdevices.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
index 66fa8c9..c745a26 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
@@ -109,6 +109,12 @@
                              <&gpio2 6 GPIO_ACTIVE_LOW>;
        };
 
+       /* fixed clock dedicated to SPI CAN controller */
+       clk20m: oscillator {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <20000000>;
+       };
 };
 
 &A53_0 {
@@ -162,7 +168,7 @@
        #size-cells = <0>;
        fsl,spi-num-chipselects = <1>;
        pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
+       pinctrl-0 = <&pinctrl_ecspi2>;
        cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
        status = "okay";
 
@@ -173,6 +179,29 @@
        };
 };
 
+&ecspi3 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi3>;
+       status = "okay";
+
+       can0: can@0 {
+               compatible = "microchip,mcp2518fd";
+               clocks = <&clk20m>;
+               gpio-controller;
+               interrupt-parent = <&gpio5>;
+               interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
+               microchip,clock-allways-on;
+               microchip,clock-out-div = <1>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_can0_int>;
+               reg = <0>;
+               spi-max-frequency = <2000000>;
+       };
+};
+
 &fec1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_fec1>;
@@ -600,6 +629,12 @@
                >;
        };
 
+       pinctrl_can0_int: can1intgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26               0x1c4
+               >;
+       };
+
        pinctrl_csi: csi_grp {
                fsl,pins = <
                        MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1      0x59
@@ -611,12 +646,16 @@
                        MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK            0x82
                        MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI            0x82
                        MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO            0x82
+                       MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13              0x40000
                >;
        };
 
-       pinctrl_ecspi2_cs: ecspi2cs {
+       pinctrl_ecspi3: ecspi3grp {
                fsl,pins = <
-                       MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13              0x40000
+                       MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK              0x4
+                       MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI              0x4
+                       MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO              0x1c4
+                       MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25               0x1c4
                >;
        };