MLK-11853 ARM: dts: imx6qp-sabreauto: remove the enet pin reconfig

Tuning MMDC ZQ_PU_OFFSET impact DDR IO timing like the value is greater
than 0x9 causing enet lost packets due to the worse timing. Reinforce
ENET DDR IO drive strength can fix the issue. Use the default pin setting
can match the RGMII timing for AI board.

Worse timing cause performance drop, the performance has no drop after
enhancing the DDR IO pins drive strength. Pass over night test.

Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit: 5ceb746c0358c0851187a3f4f6f61d02e951eae0)

Conflicts:
	arch/arm/boot/dts/imx6qp-sabreauto.dts

diff --git a/arch/arm/boot/dts/imx6qp-sabreauto.dts b/arch/arm/boot/dts/imx6qp-sabreauto.dts
index db51a73..ded0cdb 100644 (file)
--- a/arch/arm/boot/dts/imx6qp-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6qp-sabreauto.dts
@@ -79,31 +79,6 @@
        };
 };
 
-&iomuxc {
-       imx6qdl-sabreauto {
-               pinctrl_enet: enetgrp {
-                       fsl,pins = <
-                               MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
-                               MX6QDL_PAD_KEY_COL2__ENET_MDC           0x1b0b0
-                               MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b018
-                               MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b018
-                               MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b018
-                               MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b018
-                               MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b018
-                               MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b018
-                               MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b018
-                               MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b018
-                               MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b018
-                               MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b018
-                               MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b018
-                               MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b018
-                               MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
-                               MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
-                       >;
-               };
-       };
-};
-
 &pcie {
        reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;
        status = "okay";