MLK-20171: mtd: flexspi: reset flexspi FLASHxCR2 registers during probe

Flexspi registers cannot be reset to default value, reset all FLASHxCR2
registers to 0 to avoid read data with invalid LUT commands.

Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>

diff --git a/drivers/mtd/spi-nor/fsl-flexspi.c b/drivers/mtd/spi-nor/fsl-flexspi.c
index 8b1310f..3ec316e 100644 (file)
--- a/drivers/mtd/spi-nor/fsl-flexspi.c
+++ b/drivers/mtd/spi-nor/fsl-flexspi.c
@@ -930,7 +930,6 @@ static int fsl_flexspi_init_rpm(struct fsl_flexspi *flex)
 static int fsl_flexspi_nor_setup(struct fsl_flexspi *flex)
 {
        void __iomem *base = flex->iobase;
-       u32 reg;
 
        /* Reset the module */
        writel(FLEXSPI_MCR0_SWRST_MASK, base + FLEXSPI_MCR0);
@@ -945,8 +944,11 @@ static int fsl_flexspi_nor_setup(struct fsl_flexspi *flex)
        writel(FLEXSPI_MCR0_AHB_TIMEOUT_MASK | FLEXSPI_MCR0_IP_TIMEOUT_MASK |
               FLEXSPI_MCR0_OCTCOMB_EN_MASK, base + FLEXSPI_MCR0);
 
-       /* Read the register value */
-       reg = readl(base + FLEXSPI_MCR0);
+       /* Reset the FLASHxCR2 */
+       writel(0, base + FLEXSPI_FLSHA1CR2);
+       writel(0, base + FLEXSPI_FLSHA2CR2);
+       writel(0, base + FLEXSPI_FLSHB1CR2);
+       writel(0, base + FLEXSPI_FLSHB2CR2);
 
        /* Init the LUT table. */
        fsl_flexspi_init_lut(flex);