MLK-23600-1 Change MIPI CSI clock to 266MHz for dual ISP cameras

Set MIPI clock according to IC team.
for 1 ISP camera on CSI0, MIPI CSI clock set to 500MHz
for 2 ISP cameras on CSI0/CSI1, MIPI CSI clock both set to 266MHz

Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Guoniu.zhou <guoniu.zhou@nxp.com>
(cherry picked from commit a38f457b63fa8a0d9b4c5de39a12959c172e7e35)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts
index 1e3616d..1bd1dc2 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-basler.dts
@@ -86,6 +86,9 @@
 
 &mipi_csi_0 {
        status = "okay";
+       clock-frequency = <266000000>;
+       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>;
+       assigned-clock-rates = <266000000>;
 
        port@0 {
                reg = <0>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts
index 6246158..c08daa2 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-dual-ov2775.dts
@@ -103,6 +103,9 @@
 
 &mipi_csi_0 {
        status = "okay";
+       clock-frequency = <266000000>;
+       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>;
+       assigned-clock-rates = <266000000>;
 
        port@0 {
                endpoint {

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index b210cd3..9e49db7 100755 (executable)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1568,7 +1568,7 @@
                                                      "media_blk_csi_pclk",
                                                      "media_blk_csi_aclk";
                                        assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
-                                       assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
+                                       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>;
                                        assigned-clock-rates = <266000000>;
                                        bus-width = <4>;
                                        csi-gpr = <&mediamix_gasket1>;