MX7ULP needs to have the QSPI interrupt configured as a wakeup source
in the SIM_WKPU_WAKEUP_ENABLE register, otherwise the QSPI interrupts
do not wakeup the CPU from idle mode leading to poor performance in
Linux.
The SIM_WKPU_WAKEUP_ENABLE register only exists in B0 silicon, so
make sure to only write to this register in the B0 version (or greater).
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
(cherry picked from commit
1ab33446d6843f560fb6d14c781f6417225f8f3d)
(cherry picked from commit
8116f34387f8164dd72656fb8278e6df9fdf4c05)
#define SIM_SOPT1_PMIC_STBY_REQ (1<<2)
#define SIM_SOPT1_A7_SW_RESET (1<<0)
+#define WKPU_WAKEUP_EN 0x88
+#define WKPU_QSPI_CHANNEL BIT(20)
+
#define IOMUXC_PCR_MUX_ALT_SHIFT (8)
#define IOMUXC_PCR_MUX_ALT_MASK (0xF00)
#define IOMUXC_PSMI_IMUX_ALT_SHIFT (0)
writel(0x03000003, (PCC1_RBASE + 0x94));
writel(0x43000003, (PCC1_RBASE + 0x94));
}
+
+ /* Enable QSPI as a wakeup source on B0 */
+ if (soc_rev() >= CHIP_REV_2_0)
+ setbits_le32(SIM0_RBASE + WKPU_WAKEUP_EN, WKPU_QSPI_CHANNEL);
return 0;
}
#endif