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MLK-17200-3 mx7ulp: Select the SCG1 APLL PFD as a system clock source
authorYe Li <ye.li@nxp.com>
Wed, 13 Dec 2017 06:22:09 +0000 (00:22 -0600)
committerYe Li <ye.li@nxp.com>
Fri, 24 May 2019 11:28:41 +0000 (04:28 -0700)
Due to the APLL out glitch issue TKT332232, the APLLCFG PLLS bit must be set
to select SCG1 APLL PFD for generating system clock to align with the design.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 242823400c5bd59960e1b40d941e177e8ebad57e)
(cherry picked from commit 3c8d8b0a95f8b1132e301e7e00955846b12aa4cc)

board/freescale/mx7ulp_evk/imximage.cfg patch | blob | history
board/freescale/mx7ulp_evk/plugin.S patch | blob | history

diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg
index d4f6c3c..6bc7c19 100644 (file)
--- a/board/freescale/mx7ulp_evk/imximage.cfg
+++ b/board/freescale/mx7ulp_evk/imximage.cfg
@@ -45,7 +45,7 @@ DATA 4   0x403f00dc 0x00000000
 DATA 4   0x403e0040 0x01000020
 DATA 4   0x403e0500 0x01000000
 DATA 4   0x403e050c 0x80808080
-DATA 4   0x403e0508 0x00160000
+DATA 4   0x403e0508 0x00160002
 DATA 4   0x403E0510 0x00000002
 DATA 4   0x403E0514 0x00000005
 DATA 4   0x403e0500 0x00000001
diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S
index ccd2fc0..55dfecc 100644 (file)
--- a/board/freescale/mx7ulp_evk/plugin.S
+++ b/board/freescale/mx7ulp_evk/plugin.S
@@ -18,7 +18,7 @@
 
        ldr r3, =0x80808080
        str r3, [r2, #0x50c]
-       ldr r3, =0x00160000
+       ldr r3, =0x00160002
        str r3, [r2, #0x508]
        ldr r3, =0x00000002
        str r3, [r2, #0x510]