KVM: s390: protvirt: Mask PSW interrupt bits for interception 104 and 112
authorJanosch Frank <frankja@linux.ibm.com>
Fri, 13 Dec 2019 13:26:06 +0000 (08:26 -0500)
committerChristian Borntraeger <borntraeger@de.ibm.com>
Thu, 27 Feb 2020 18:47:12 +0000 (19:47 +0100)
We're not allowed to inject interrupts on intercepts that leave the
guest state in an "in-between" state where the next SIE entry will do a
continuation, namely secure instruction interception (104) and secure
prefix interception (112).
As our PSW is just a copy of the real one that will be replaced on the
next exit, we can mask out the interrupt bits in the PSW to make sure
that we do not inject anything.

Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
[borntraeger@de.ibm.com: patch merging, splitting, fixing]
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
arch/s390/kvm/kvm-s390.c

index 028ce4e..66ba6ca 100644 (file)
@@ -4093,6 +4093,7 @@ static int vcpu_post_run(struct kvm_vcpu *vcpu, int exit_reason)
        return vcpu_post_run_fault_in_sie(vcpu);
 }
 
+#define PSW_INT_MASK (PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_MCHECK)
 static int __vcpu_run(struct kvm_vcpu *vcpu)
 {
        int rc, exit_reason;
@@ -4129,6 +4130,16 @@ static int __vcpu_run(struct kvm_vcpu *vcpu)
                        memcpy(vcpu->run->s.regs.gprs,
                               sie_page->pv_grregs,
                               sizeof(sie_page->pv_grregs));
+                       /*
+                        * We're not allowed to inject interrupts on intercepts
+                        * that leave the guest state in an "in-between" state
+                        * where the next SIE entry will do a continuation.
+                        * Fence interrupts in our "internal" PSW.
+                        */
+                       if (vcpu->arch.sie_block->icptcode == ICPT_PV_INSTR ||
+                           vcpu->arch.sie_block->icptcode == ICPT_PV_PREF) {
+                               vcpu->arch.sie_block->gpsw.mask &= ~PSW_INT_MASK;
+                       }
                }
                local_irq_disable();
                __enable_cpu_timer_accounting(vcpu);