#define EASRC_CC_INSIGN_MASK BIT(EASRC_CC_INSIGN_SHIFT)
#define EASRC_CC_INSIGN BIT(EASRC_CC_INSIGN_SHIFT)
#define EASRC_CC_CHEN_SHIFT 0
-#define EASRC_CC_CHEN_WIDTH 4
+#define EASRC_CC_CHEN_WIDTH 5
#define EASRC_CC_CHEN_MASK ((BIT(EASRC_CC_CHEN_WIDTH) - 1) \
<< EASRC_CC_CHEN_SHIFT)
#define EASRC_CC_CHEN(v) (((v) << EASRC_CC_CHEN_SHIFT) \
/* ASRC Control Output Access (COA) */
#define EASRC_COA_ITER_SHIFT 16
-#define EASRC_COA_ITER_WIDTH 5
+#define EASRC_COA_ITER_WIDTH 6
#define EASRC_COA_ITER_MASK ((BIT(EASRC_COA_ITER_WIDTH) - 1) \
<< EASRC_COA_ITER_SHIFT)
#define EASRC_COA_ITER(v) (((v) << EASRC_COA_ITER_SHIFT) \
& EASRC_COA_ITER_MASK)
#define EASRC_COA_GRLEN_SHIFT 8
-#define EASRC_COA_GRLEN_WIDTH 5
+#define EASRC_COA_GRLEN_WIDTH 6
#define EASRC_COA_GRLEN_MASK ((BIT(EASRC_COA_GRLEN_WIDTH) - 1) \
<< EASRC_COA_GRLEN_SHIFT)
#define EASRC_COA_GRLEN(v) (((v) << EASRC_COA_GRLEN_SHIFT) \
& EASRC_COA_GRLEN_MASK)
#define EASRC_COA_ACCLEN_SHIFT 0
-#define EASRC_COA_ACCLEN_WIDTH 5
+#define EASRC_COA_ACCLEN_WIDTH 6
#define EASRC_COA_ACCLEN_MASK ((BIT(EASRC_COA_ACCLEN_WIDTH) - 1) \
<< EASRC_COA_ACCLEN_SHIFT)
#define EASRC_COA_ACCLEN(v) (((v) << EASRC_COA_ACCLEN_SHIFT) \