MLK-11117-01 ARM: clk: imx6: adjust axi clock to 264MHz on imx6ul

According to the latest reference manual, the default AXI clock rate
should be 264MHz. Soucre AXI/AHB from pll2_bus to get the required
clock rate.

Signed-off-by: Bai Ping <b51503@freescale.com>
(cherry picked from commit d7560da7baee7a14ecb33d51182bbdc485ee6d7d)

diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index 30f6532..9d088e0 100644 (file)
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -450,6 +450,17 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
        clk_set_parent(clks[IMX6UL_CLK_SIM_PRE_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]);
 
        clk_set_parent(clks[IMX6UL_CLK_ENFC_SEL], clks[IMX6UL_CLK_PLL2_PFD2]);
+
+       /* Lower the AHB clock rate before changing the clock source. */
+       imx_clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000);
+
+       /* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */
+       imx_clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]);
+       imx_clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_CLK2]);
+       imx_clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE], clks[IMX6UL_CLK_PLL2_BUS]);
+       imx_clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_PRE]);
+
+       imx_clk_set_rate(clks[IMX6UL_CLK_AHB], 132000000);
 }
 
 CLK_OF_DECLARE(imx6ul, "fsl,imx6ul-ccm", imx6ul_clocks_init);