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MGS-5584 arm64: imx8mn.dtsi: GPU reg format should align with soc0.
authorElla Feng <ella.feng@nxp.com>
Wed, 25 Mar 2020 10:33:34 +0000 (18:33 +0800)
committerDong Aisheng <aisheng.dong@nxp.com>
Mon, 14 Dec 2020 03:22:15 +0000 (11:22 +0800)
GPU node is now within soc0 node, reg format need follow
“#address-cells = <1>;#size-cells = <1>;” as soc0.

Signed-off-by: Ella Feng <ella.feng@nxp.com>
arch/arm64/boot/dts/freescale/imx8mn.dtsi patch | blob | history

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 633cdcb..d06b251 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -1295,9 +1295,9 @@
 
                gpu: gpu@38000000 {
                        compatible = "fsl,imx8mn-gpu", "fsl,imx6q-gpu";
-                       reg = <0x0 0x38000000 0x0 0x40000>,
-                             <0x0 0x40000000 0x0 0x80000000>,
-                             <0x0 0x0 0x0 0x8000000>;
+                       reg = <0x38000000 0x40000>,
+                             <0x40000000 0x80000000>,
+                             <0x0 0x8000000>;
                        reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem";
                        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "irq_3d";