MLK-17119 i.MX8QM DDR4 ARM2 Support

Add support for DDR4 board in u-boot.
Main changes are the SD card slot and ddr
type

Signed-off-by: Teo Hall <teo.hall@nxp.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c5e2803..afd1a5b 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -391,6 +391,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \
                fsl-imx8mq-ddr4-arm2.dtb
 
 dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qm-lpddr4-arm2.dtb \
+               fsl-imx8qm-ddr4-arm2.dtb \
                fsl-imx8qm-mek.dtb \
                fsl-imx8qxp-lpddr4-arm2.dtb \
                fsl-imx8qxp-mek.dtb

diff --git a/arch/arm/dts/fsl-imx8qm-ddr4-arm2.dts b/arch/arm/dts/fsl-imx8qm-ddr4-arm2.dts
new file mode 100644 (file)
index 0000000..2f5b453
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm-ddr4-arm2.dts
@@ -0,0 +1,420 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/memreserve/ 0x80000000 0x00020000;
+
+#include "fsl-imx8qm.dtsi"
+
+/ {
+       model = "Freescale i.MX8QM ARM2";
+       compatible = "fsl,imx8qm-arm2", "fsl,imx8qm";
+
+       chosen {
+               bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
+               stdout-path = &lpuart0;
+       };
+
+       leds {
+               compatible = "gpio-leds";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_gpio_leds>;
+               user {
+                       label = "heartbeat";
+                       gpios = <&gpio2 15 0>;
+                       default-state = "on";
+                       linux,default-trigger = "heartbeat";
+               };
+       };
+
+       regulators {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               reg_usb_otg1_vbus: regulator@0 {
+                       compatible = "regulator-fixed";
+                       reg = <0>;
+                       regulator-name = "usb_otg1_vbus";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+               };
+
+               reg_usdhc2_vmmc: usdhc2_vmmc {
+                       compatible = "regulator-fixed";
+                       regulator-name = "sw-3p3-sd1";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+               };
+
+       };
+
+};
+
+&iomuxc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_hog_1>;
+
+       imx8qm-arm2 {
+               pinctrl_hog_1: hoggrp-1 {
+                       fsl,pins = <
+                               SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03          0x06000048
+                       >;
+               };
+
+               pinctrl_fec1: fec1grp {
+                       fsl,pins = <
+                               SC_P_ENET0_MDC_CONN_ENET0_MDC                   0x06000048
+                               SC_P_ENET0_MDIO_CONN_ENET0_MDIO                 0x06000048
+                               SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048
+                               SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC       0x06000048
+                               SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0     0x06000048
+                               SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1     0x06000048
+                               SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2     0x06000048
+                               SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3     0x06000048
+                               SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC       0x06000048
+                               SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048
+                               SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0     0x06000048
+                               SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1     0x06000048
+                               SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2     0x06000048
+                               SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3     0x06000048
+                       >;
+               };
+
+               pinctrl_fec2: fec2grp {
+                       fsl,pins = <
+                               SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000048
+                               SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC       0x06000048
+                               SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0     0x06000048
+                               SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1     0x06000048
+                               SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2     0x06000048
+                               SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3     0x06000048
+                               SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC       0x06000048
+                               SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000048
+                               SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0     0x06000048
+                               SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1     0x06000048
+                               SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2     0x06000048
+                               SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3     0x06000048
+                       >;
+               };
+
+               pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
+                       fsl,pins = <
+                               SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL      0xc600004c
+                               SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA      0xc600004c
+                       >;
+               };
+
+               pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp {
+                       fsl,pins = <
+                               SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL      0xc600004c
+                               SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA      0xc600004c
+                       >;
+               };
+
+               pinctrl_lpuart0: lpuart0grp {
+                       fsl,pins = <
+                               SC_P_UART0_RX_DMA_UART0_RX              0x06000020
+                               SC_P_UART0_TX_DMA_UART0_TX              0x06000020
+                       >;
+               };
+
+
+
+               pinctrl_usdhc3_gpio: usdhc3grpgpio {
+                       fsl,pins = <
+                               SC_P_USDHC2_RESET_B_CONN_USDHC2_RESET_B 0x00000021
+                       >;
+               };
+
+               pinctrl_usdhc3: usdhc3grp {
+                       fsl,pins = <
+                               SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000041
+                               SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000021
+                               SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000021
+                               SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000021
+                               SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2     0x00000021
+                               SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3     0x00000021
+                                SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021
+                               /* WP */
+                               SC_P_USDHC2_WP_LSIO_GPIO4_IO11          0x00000021
+                               /* CD */
+                               SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12        0x00000021
+                       >;
+               };
+                pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+                        fsl,pins = <
+                                SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000040
+                               SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000020
+                               SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000020
+                               SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000020
+                               SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2     0x00000020
+                               SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3     0x00000020
+                                SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
+                               /* WP */
+                               SC_P_USDHC2_WP_LSIO_GPIO4_IO11          0x00000020
+                               /* CD */
+                               SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12        0x00000020
+                       >;
+               };
+                pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+                        fsl,pins = <
+                                SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000040
+                               SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000020
+                               SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000020
+                               SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000020
+                               SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2     0x00000020
+                               SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3     0x00000020
+                                SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
+                               /* WP */
+                               SC_P_USDHC2_WP_LSIO_GPIO4_IO11          0x00000020
+                               /* CD */
+                               SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12        0x00000020
+                       >;
+               };
+
+
+               pinctrl_lpi2c1: lpi2c1grp {
+                       fsl,pins = <
+                               SC_P_GPT0_CLK_DMA_I2C1_SCL              0x06000020
+                               SC_P_GPT0_CAPTURE_DMA_I2C1_SDA          0x06000020
+                               /*
+                                * Change the default alt function from SCL/SDA to others,
+                                * to avoid select input conflict with GPT0
+                                */
+                               SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03        0x0700004c
+                               SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04        0x0700004c
+                               SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05        0x0700004c
+                               SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06        0x0700004c
+                       >;
+               };
+
+               pinctrl_lpspi0: lpspi0grp {
+                       fsl,pins = <
+                               SC_P_SPI0_SCK_DMA_SPI0_SCK              0x0600004c
+                               SC_P_SPI0_SDO_DMA_SPI0_SDO              0x0600004c
+                               SC_P_SPI0_SDI_DMA_SPI0_SDI              0x0600004c
+                               SC_P_SPI0_CS0_DMA_SPI0_CS0              0x0600004c
+                               SC_P_SPI0_CS1_DMA_SPI0_CS1              0x0600004c
+                       >;
+               };
+
+               pinctrl_flexspi0: flexspi0grp {
+                       fsl,pins = <
+                               SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0     0x0600004c
+                               SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1     0x0600004c
+                               SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2     0x0600004c
+                               SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3     0x0600004c
+                               SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS         0x0600004c
+                               SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B     0x0600004c
+                               SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B     0x0600004c
+                               SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK       0x0600004c
+                               SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK       0x0600004c
+                               SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0     0x0600004c
+                               SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1     0x0600004c
+                               SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2     0x0600004c
+                               SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3     0x0600004c
+                               SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS         0x0600004c
+                               SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B     0x0600004c
+                               SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B     0x0600004c
+                       >;
+               };
+
+               pinctrl_gpio_leds: gpioledsgrp {
+                       fsl,pins = <
+                               SC_P_SPDIF0_TX_LSIO_GPIO2_IO15          0x00000021
+                       >;
+               };
+       };
+};
+
+&gpio2 {
+       status = "okay";
+};
+
+&gpio4 {
+       status = "okay";
+};
+
+&usdhc3 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>;
+       pinctrl-1 = <&pinctrl_usdhc3_100mhz>,<&pinctrl_usdhc3_gpio>;
+       pinctrl-2 = <&pinctrl_usdhc3_200mhz>,<&pinctrl_usdhc3_gpio>;
+       bus-width = <4>;
+       cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
+       wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
+        no-1-8-v;
+       status = "okay";
+
+};
+
+&usbotg1 {
+       vbus-supply = <&reg_usb_otg1_vbus>;
+       srp-disable;
+       hnp-disable;
+       adp-disable;
+       disable-over-current;
+       status = "okay";
+};
+
+&usb2 {
+       status = "okay";
+};
+
+&fec1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec1>;
+       phy-mode = "rgmii";
+       phy-handle = <&ethphy0>;
+       fsl,ar8031-phy-fixup;
+       fsl,magic-packet;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy0: ethernet-phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <0>;
+               };
+
+               ethphy1: ethernet-phy@1 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <1>;
+               };
+       };
+};
+
+&fec2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec2>;
+       phy-mode = "rgmii";
+       phy-handle = <&ethphy1>;
+       fsl,ar8031-phy-fixup;
+       fsl,magic-packet;
+       status = "okay";
+};
+
+&flexspi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexspi0>;
+       status = "okay";
+
+       flash0: mt35xu512aba@0 {
+               reg = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               spi-max-frequency = <29000000>;
+               spi-nor,ddr-quad-read-dummy = <8>;
+       };
+};
+
+&i2c1 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lpi2c1>;
+       status = "okay";
+
+       pca9557_a: gpio@18 {
+               compatible = "nxp,pca9557";
+               reg = <0x18>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       pca9557_b: gpio@19 {
+               compatible = "nxp,pca9557";
+               reg = <0x19>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       pca9557_c: gpio@1b {
+               compatible = "nxp,pca9557";
+               reg = <0x1b>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+
+       pca9557_d: gpio@1f {
+               compatible = "nxp,pca9557";
+               reg = <0x1f>;
+               gpio-controller;
+               #gpio-cells = <2>;
+       };
+};
+
+&i2c1_lvds0 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
+       clock-frequency = <100000>;
+       status = "okay";
+
+       it6263-0@4c {
+               compatible = "ITE,it6263";
+               reg = <0x4c>;
+       };
+};
+
+&i2c1_lvds1 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lvds1_lpi2c1>;
+       clock-frequency = <100000>;
+       status = "okay";
+
+       it6263-1@4c {
+               compatible = "ITE,it6263";
+               reg = <0x4c>;
+       };
+};
+
+&lpspi0 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lpspi0>;
+       status = "okay";
+
+       spidev0: spi@0 {
+               reg = <0>;
+               compatible = "rohm,dh2228fv";
+               spi-max-frequency = <4000000>;
+       };
+};
+
+&lpuart0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lpuart0>;
+       status = "okay";
+};
+
+&lpuart1 {
+       status = "okay";
+};
+

diff --git a/board/freescale/imx8qm_arm2/imx8qm_arm2.c b/board/freescale/imx8qm_arm2/imx8qm_arm2.c
index 1b730f8..61db268 100644 (file)
--- a/board/freescale/imx8qm_arm2/imx8qm_arm2.c
+++ b/board/freescale/imx8qm_arm2/imx8qm_arm2.c
@@ -102,8 +102,8 @@ int board_early_init_f(void)
 static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 #ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2
        {USDHC1_BASE_ADDR, 0, 8},
-#endif
        {USDHC2_BASE_ADDR, 0, 4},
+#endif
        {USDHC3_BASE_ADDR, 0, 4},
 };
 
@@ -122,8 +122,6 @@ static iomux_cfg_t emmc0[] = {
        SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
        SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
 };
-#endif
-
 static iomux_cfg_t usdhc1_sd[] = {
        SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
        SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
@@ -136,7 +134,7 @@ static iomux_cfg_t usdhc1_sd[] = {
        SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
        SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
 };
-
+#endif
 static iomux_cfg_t usdhc2_sd[] = {
        SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
        SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
@@ -173,9 +171,6 @@ int board_mmc_init(bd_t *bis)
                        usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
                        break;
                case 1:
-#else
-               case 0:
-#endif
                        if (!power_domain_lookup_name("conn_sdhc1", &pd))
                                power_domain_on(&pd);
 
@@ -185,11 +180,11 @@ int board_mmc_init(bd_t *bis)
                        gpio_request(USDHC1_CD_GPIO, "sd1_cd");
                        gpio_direction_input(USDHC1_CD_GPIO);
                        break;
-#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2
                case 2:
 #else
-               case 1:
+               case 0:
 #endif
+
                        if (!power_domain_lookup_name("conn_sdhc2", &pd))
                                power_domain_on(&pd);
 
@@ -221,7 +216,11 @@ int board_mmc_getcd(struct mmc *mmc)
 
        switch (cfg->esdhc_base) {
        case USDHC1_BASE_ADDR:
+#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2
                ret = 1; /* eMMC */
+#else
+                ret = 0; /* eMMC not present on DDR4 board */
+#endif
                break;
        case USDHC2_BASE_ADDR:
                ret = !gpio_get_value(USDHC1_CD_GPIO);
@@ -553,7 +552,7 @@ int board_mmc_get_env_dev(int devno)
 #ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2
        return devno;
 #else
-       return devno - 1;
+       return devno - 2;
 #endif
 }
 
@@ -562,7 +561,7 @@ int mmc_map_to_kernel_blk(int dev_no)
 #ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2
        return dev_no;
 #else
-       return dev_no + 1;
+       return dev_no + 2;
 #endif
 }
 

diff --git a/configs/imx8qm_ddr4_arm2_defconfig b/configs/imx8qm_ddr4_arm2_defconfig
new file mode 100644 (file)
index 0000000..d15857b
--- /dev/null
+++ b/configs/imx8qm_ddr4_arm2_defconfig
@@ -0,0 +1,73 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-ddr4-arm2"
+CONFIG_TARGET_IMX8QM_DDR4_ARM2=y
+CONFIG_CMD_IMPORTENV=n
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DM=y
+CONFIG_CMD_CACHE=y
+
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM_I2C=y
+# CONFIG_DM_I2C_COMPAT is not set
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_CMD_I2C=y
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+
+CONFIG_CMD_GPIO=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_BOOTDELAY=3
+CONFIG_IMX_BOOTAUX=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MMC=y
+CONFIG_DM_MMC=y
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_FSL_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_4BYTES_ADDR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_DM_ETH=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+
+CONFIG_VIDEO=y
+
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SC_THERMAL=y

diff --git a/include/configs/imx8qm_arm2.h b/include/configs/imx8qm_arm2.h
index bd97526..827cc3c 100644 (file)
--- a/include/configs/imx8qm_arm2.h
+++ b/include/configs/imx8qm_arm2.h
@@ -31,7 +31,9 @@
 #define USDHC1_BASE_ADDR                0x5B010000
 #define USDHC2_BASE_ADDR                0x5B020000
 #define USDHC3_BASE_ADDR                0x5B030000
-#define CONFIG_SUPPORT_EMMC_BOOT       /* eMMC specific */
+#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2
+#define CONFIG_SUPPORT_EMMC_BOOT   /* eMMC specific */
+#endif
 
 #define CONFIG_ENV_OVERWRITE
 
@@ -135,7 +137,7 @@
        "fdt_addr=0x83000000\0"                 \
        "fdt_high=0xffffffffffffffff\0"         \
        "boot_fdt=try\0" \
-       "fdt_file=fsl-imx8qm-lpddr4-arm2.dtb\0" \
+       "fdt_file="__stringify(CONFIG_DEFAULT_DEVICE_TREE)".dtb\0" \
        "initrd_addr=0x83800000\0"              \
        "initrd_high=0xffffffffffffffff\0" \
        "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
@@ -226,13 +228,16 @@
   * On DDR4 board, USDHC1 is mux for NAND, USDHC2 is for SD, USDHC3 is for SD on base board
   */
 #ifdef CONFIG_TARGET_IMX8QM_LPDDR4_ARM2
-#define CONFIG_SYS_MMC_ENV_DEV         1   /* USDHC2 */
-#define CONFIG_MMCROOT                 "/dev/mmcblk1p2"  /* USDHC2 */
+#define CONFIG_SYS_MMC_ENV_DEV         1   /* USDHC1 */
+#define CONFIG_MMCROOT                 "/dev/mmcblk1p2"  /* USDHC1 */
 #define CONFIG_SYS_FSL_USDHC_NUM       3
+
 #else
+
 #define CONFIG_SYS_MMC_ENV_DEV         0   /* USDHC2 */
-#define CONFIG_MMCROOT                 "/dev/mmcblk1p2"  /* USDHC2 */
-#define CONFIG_SYS_FSL_USDHC_NUM       2
+#define CONFIG_MMCROOT                 "/dev/mmcblk2p2"  /* USDHC2 */
+#define CONFIG_SYS_FSL_USDHC_NUM       1
+
 #endif
 
 /* Size of malloc() pool */