*/
&dma_subsys {
+ lpuart4: serial@5a0a0000 {
+ compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
+ reg = <0x5a0a0000 0x1000>;
+ interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&uart4_lpcg 1>, <&uart4_lpcg 0>;
+ clock-names = "ipg", "baud";
+ assigned-clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <80000000>;
+ power-domains = <&pd IMX_SC_R_UART_4>;
+ power-domain-names = "uart";
+ dma-names = "tx","rx";
+ dmas = <&edma2 21 0 0>,
+ <&edma2 20 0 1>;
+ status = "disabled";
+ };
+
uart4_lpcg: clock-controller@5a4a0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a4a0000 0x10000>;
&lpuart1 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
- power-domains = <&pd IMX_SC_R_UART_1>;
dmas = <&edma2 15 0 0>,
<&edma2 14 0 1>;
};
&lpuart2 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
+ dmas = <&edma2 17 0 0>,
+ <&edma2 16 0 1>;
};
&lpuart3 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
+ dmas = <&edma2 19 0 0>,
+ <&edma2 18 0 1>;
};
&i2c0 {