memset(state, 0, sizeof(state_struct));
mutex_init(&state->mutex);
- state->mem.regs_base = hdp->regs_base;
- state->mem.ss_base = hdp->ss_base;
+ state->mem = &hdp->mem;
state->rw = hdp->rw;
}
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
val |= 0x2;
- writel(val, hdp->ss_base + CSR_PIXEL_LINK_MUX_CTL);
+ writel(val, hdp->mem.ss_base + CSR_PIXEL_LINK_MUX_CTL);
}
int imx8qm_pixel_link_init(state_struct *state)
/* register map */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- hdp->regs_base = devm_ioremap_resource(dev, res);
- if (IS_ERR(hdp->regs_base)) {
+ hdp->mem.regs_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(hdp->mem.regs_base)) {
dev_err(dev, "Failed to get HDP CTRL base register\n");
return -EINVAL;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- hdp->ss_base = devm_ioremap_resource(dev, res);
- if (IS_ERR(hdp->ss_base)) {
+ hdp->mem.ss_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(hdp->mem.ss_base)) {
dev_err(dev, "Failed to get HDP CRS base register\n");
return -EINVAL;
}
struct edid *edid;
char cable_state;
- void __iomem *regs_base; /* Controller regs base */
- void __iomem *ss_base; /* HDP Subsystem regs base */
+ struct hdp_mem mem;
u8 is_edid;
u8 is_4kp60;
int vic;
int irq[HPD_IRQ_NUM];
struct delayed_work hotplug_work;
-
};
u32 imx_hdp_audio(AUDIO_TYPE type, u32 sample_rate, u32 channels, u32 width);