ARM: dts: imx6ul: use nvmem-cells for cpu speed grading

On i.MX6UL, accessing OCOTP directly is wrong because the ocotp clock
needs to be enabled first, so use the nvmem-cells binding instead.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
(cherry picked from commit 44dca5db09efe6e03e5c50e2e093d823d9f0ffee)

diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index f585db3..5f4a2a5 100644 (file)
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -94,6 +94,8 @@
                                      "pll1_bypass_src", "osc";
                        arm-supply = <&reg_arm>;
                        soc-supply = <&reg_soc>;
+                       nvmem-cells = <&cpu_speed_grade>;
+                       nvmem-cell-names = "speed_grade";
                };
        };
 
@@ -1126,6 +1128,10 @@
                                tempmon_temp_grade: temp-grade@20 {
                                        reg = <0x20 4>;
                                };
+
+                               cpu_speed_grade: speed-grade@10 {
+                                       reg = <0x10 4>;
+                               };
                        };
 
                        csu: csu@021c0000 {