<&clk IMX8MN_SYS_PLL1_800M>;
assigned-clock-rate = <594000000>, <500000000>, <200000000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- lcdif-gpr = <&dispmix_gpr>;
resets = <&lcdif_resets>;
power-domains = <&dispmix_pd>;
status = "disabled";
<&clk IMX8MN_VIDEO_PLL1_OUT>;
assigned-clock-rates = <266000000>, <594000000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- dsi-gpr = <&dispmix_gpr>;
resets = <&mipi_dsi_resets>;
power-domains = <&mipi_pd>;
status = "disabled";
assigned-clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
<&clk IMX8MN_CLK_DISP_APB_ROOT>;
assigned-clock-rates = <500000000>, <200000000>;
- isi-gpr = <&dispmix_gpr>;
resets = <&isi_resets>;
status = "disabled";
};
<&clk IMX8MN_SYS_PLL2_1000M>;
assigned-clock-rates = <333000000>, <125000000>;
bus-width = <4>;
- csi-gpr = <&dispmix_gpr>;
+ csi-gpr = <&mipi2csi_gasket>;
power-domains = <&mipi_pd>;
resets = <&mipi_csi_resets>;
status = "disabled";
};
};
- dispmix_gpr: display-gpr@32e28000 {
- compatible = "fsl, imx8mm-iomuxc-gpr", "syscon";
- reg = <0x0 0x32e28000 0x0 0x8000>;
+ mipi2csi_gasket: gasket@32e28060 {
+ compatible = "syscon";
+ reg = <0x0 0x32e28060 0x0 0x28>;
};
dispmix-reset {
}
}
-static void dump_disp_mix_regs(struct csi_state *state, const char *label)
+static void dump_gasket_regs(struct csi_state *state, const char *label)
{
struct {
u32 offset;
const char * const name;
} registers[] = {
- { 0x00, "DISP_SFT_RSTN_CSR" },
- { 0x04, "DISP_CLK_EN_CSR" },
- { 0x08, "GPR_MIPI_RESET_DIV" },
{ 0x60, "GPR_GASKET_0_CTRL" },
{ 0x64, "GPR_GASKET_0_HSIZE" },
{ 0x68, "GPR_GASKET_0_VSIZE" },
v4l2_dbg(2, debug, &state->sd, "--- %s ---\n", label);
for (i = 0; i < ARRAY_SIZE(registers); i++) {
- regmap_read(state->gpr, registers[i].offset, &cfg);
+ regmap_read(state->gasket, registers[i].offset, &cfg);
v4l2_dbg(2, debug, &state->sd, "%20s[%x]: 0x%.8x\n", registers[i].name, registers[i].offset, cfg);
}
}
static void disp_mix_gasket_config(struct csi_state *state)
{
- struct regmap *gpr = state->gpr;
+ struct regmap *gasket = state->gasket;
struct csis_pix_format const *fmt = state->csis_fmt;
struct v4l2_mbus_framefmt *mf = &state->format;
s32 fmt_val = -EINVAL;
return;
}
- regmap_read(gpr, DISP_MIX_GASKET_0_CTRL, &val);
+ regmap_read(gasket, DISP_MIX_GASKET_0_CTRL, &val);
if (fmt_val == GASKET_0_CTRL_DATA_TYPE_YUV422_8)
val |= GASKET_0_CTRL_DUAL_COMP_ENABLE;
val |= GASKET_0_CTRL_DATA_TYPE(fmt_val);
- regmap_write(gpr, DISP_MIX_GASKET_0_CTRL, val);
+ regmap_write(gasket, DISP_MIX_GASKET_0_CTRL, val);
if (WARN_ON(!mf->width || !mf->height))
return;
- regmap_write(gpr, DISP_MIX_GASKET_0_HSIZE, mf->width);
- regmap_write(gpr, DISP_MIX_GASKET_0_VSIZE, mf->height);
+ regmap_write(gasket, DISP_MIX_GASKET_0_HSIZE, mf->width);
+ regmap_write(gasket, DISP_MIX_GASKET_0_VSIZE, mf->height);
}
static void disp_mix_gasket_enable(struct csi_state *state, bool enable)
{
- struct regmap *gpr = state->gpr;
+ struct regmap *gasket = state->gasket;
if (enable)
- regmap_update_bits(gpr, DISP_MIX_GASKET_0_CTRL,
+ regmap_update_bits(gasket, DISP_MIX_GASKET_0_CTRL,
GASKET_0_CTRL_ENABLE,
GASKET_0_CTRL_ENABLE);
else
- regmap_update_bits(gpr, DISP_MIX_GASKET_0_CTRL,
+ regmap_update_bits(gasket, DISP_MIX_GASKET_0_CTRL,
GASKET_0_CTRL_ENABLE,
0);
}
mipi_csis_clear_counters(state);
mipi_csis_start_stream(state);
dump_csis_regs(state, __func__);
- dump_disp_mix_regs(state, __func__);
+ dump_gasket_regs(state, __func__);
} else {
mipi_csis_stop_stream(state);
if (debug > 0)
mipi_csis_log_counters(state, true);
if (debug) {
dump_csis_regs(state, __func__);
- dump_disp_mix_regs(state, __func__);
+ dump_gasket_regs(state, __func__);
}
mutex_unlock(&state->lock);
return 0;
}
phy_reset_fn = of_id->data;
- state->gpr = syscon_regmap_lookup_by_phandle(dev->of_node, "csi-gpr");
- if (IS_ERR(state->gpr)) {
- dev_err(dev, "failed to get csi gpr\n");
- return PTR_ERR(state->gpr);
+ state->gasket = syscon_regmap_lookup_by_phandle(dev->of_node, "csi-gpr");
+ if (IS_ERR(state->gasket)) {
+ dev_err(dev, "failed to get csi gasket\n");
+ return PTR_ERR(state->gasket);
}
ret = mipi_csis_of_parse_resets(state);