#define BM_ANADIG_ANA_MISC0_V3_STOP_MODE_CONFIG 0xc00
/* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */
#define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000
-/* i.MX6SX DISCON_HIGH_SNVS is changed to bit 12 */
+/* Since i.MX6SX, DISCON_HIGH_SNVS is changed to bit 12 */
#define BM_ANADIG_ANA_MISC0_V2_DISCON_HIGH_SNVS 0x1000
#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000
#define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000
static inline void imx_anatop_disconnect_high_snvs(bool enable)
{
- if (cpu_is_imx6sx())
+ if (cpu_is_imx6sx() || cpu_is_imx6ul())
regmap_write(anatop, ANADIG_ANA_MISC0 +
(enable ? REG_SET : REG_CLR),
BM_ANADIG_ANA_MISC0_V2_DISCON_HIGH_SNVS);
imx_anatop_enable_fet_odrive(true);
- if (cpu_is_imx6sl() || cpu_is_imx6sx())
+ if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul())
imx_anatop_disconnect_high_snvs(true);
}
imx_anatop_enable_fet_odrive(false);
- if (cpu_is_imx6sl() || cpu_is_imx6sx())
+ if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul())
imx_anatop_disconnect_high_snvs(false);
}