}
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
return 0;
}
#endif
+#endif
int board_early_init_f(void)
{
#endif
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
setup_usb();
+#else
+ /*
+ * set daisy chain for otg_pin_id on 6q.
+ * for 6dl, this bit is reserved
+ */
+ #ifdef CONFIG_SCMEVB
+ imx_iomux_set_gpr_register(1, 13, 1, 0);
+ #else
+ imx_iomux_set_gpr_register(1, 13, 1, 1);
+ #endif
+#endif
#endif
#ifdef CONFIG_PCIE_IMX
}
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
return 0;
}
#endif
+#endif
int board_early_init_f(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
setup_usb();
+#else
+ /*
+ * set daisy chain for otg_pin_id on 6q.
+ * for 6dl, this bit is reserved
+ */
+ imx_iomux_set_gpr_register(1, 13, 1, 1);
+#endif
#endif
return 0;
#endif
#ifdef CONFIG_USB_EHCI_MX6
-
+#ifndef CONFIG_DM_USB
iomux_v3_cfg_t const usb_otg_pads[] = {
MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
};
return 0;
}
#endif
+#endif
int board_early_init_f(void)
{
#endif
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
setup_usb();
+#else
+ /*
+ * Set daisy chain for otg_pin_id on 6q.
+ * For 6dl, this bit is reserved.
+ */
+ imx_iomux_set_gpr_register(1, 13, 1, 0);
+#endif
#endif
return 0;
}
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
return 0;
}
#endif
+#endif
int board_early_init_f(void)
{
#endif
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
setup_usb();
+#else
+ /*
+ * set daisy chain for otg_pin_id on 6q.
+ * for 6dl, this bit is reserved
+ */
+ imx_iomux_set_gpr_register(1, 13, 1, 0);
+#endif
#endif
#ifdef CONFIG_PCIE_IMX
#endif
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
return 0;
}
#endif
+#endif
int board_early_init_f(void)
{
#endif
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
setup_usb();
+#endif
#endif
return 0;
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
iomux_v3_cfg_t const usb_otg1_pads[] = {
return 0;
}
#endif
+#endif
int board_early_init_f(void)
{
}
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
return 0;
}
#endif
+#endif
int board_init(void)
{
#endif
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
setup_usb();
+#endif
#endif
return 0;
}
}
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
return 0;
}
#endif
+#endif
int board_init(void)
{
#endif
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
setup_usb();
#endif
+#endif
#ifdef CONFIG_FSL_QSPI
board_qspi_init();
#endif
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
return 0;
}
#endif
+#endif
int board_early_init_f(void)
{
dm_gpio_set_value(&desc, 0);
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
setup_usb();
#endif
+#endif
#ifdef CONFIG_FSL_QSPI
board_qspi_init();
#endif
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
return 0;
}
#endif
+#endif
int board_phy_config(struct phy_device *phydev)
{
#endif
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
setup_usb();
#endif
+#endif
#ifdef CONFIG_FSL_QSPI
board_qspi_init();
#endif
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
return 0;
}
#endif
+#endif
int board_phy_config(struct phy_device *phydev)
{
#endif
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
setup_usb();
#endif
+#endif
#ifdef CONFIG_FSL_QSPI
board_qspi_init();
}
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
iomux_v3_cfg_t const usb_otg1_pads[] = {
return 0;
}
#endif
+#endif
#endif
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
return 0;
}
#endif
+#endif
#ifdef CONFIG_NAND_MXS
static iomux_v3_cfg_t const nand_pads[] = {
#endif
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
setup_usb();
#endif
+#endif
#ifdef CONFIG_FSL_QSPI
board_qspi_init();
}
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
iomux_v3_cfg_t const usb_otg1_pads[] = {
return 0;
}
#endif
+#endif
}
#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
iomux_v3_cfg_t const usb_otg1_pads[] = {
return 0;
}
#endif
+#endif
#endif
#ifdef CONFIG_USB_EHCI_MX7
+#ifndef CONFIG_DM_USB
iomux_v3_cfg_t const usb_otg1_pads[] = {
MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
};
imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, ARRAY_SIZE(usb_otg2_pads));
}
#endif
+#endif
int board_early_init_f(void)
{
#endif
#ifdef CONFIG_USB_EHCI_MX7
+#ifndef CONFIG_DM_USB
setup_usb();
+#endif
#endif
return 0;
#endif
#ifdef CONFIG_USB_EHCI_MX7
+#ifndef CONFIG_DM_USB
+
iomux_v3_cfg_t const usb_otg1_pads[] = {
MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
};
imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, ARRAY_SIZE(usb_otg2_pads));
}
#endif
+#endif
int board_early_init_f(void)
{
#endif
#ifdef CONFIG_USB_EHCI_MX7
+#ifndef CONFIG_DM_USB
setup_usb();
+#endif
#endif
return 0;
}