MLK-17489-4: hdmi arc: Create new imx-arc.c file

Move hdmi arc functions to imx-arc.c from phy configuration file.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>

diff --git a/drivers/gpu/drm/imx/hdp/API_AFE_ss28fdsoi_kiran_hdmitx.c b/drivers/gpu/drm/imx/hdp/API_AFE_ss28fdsoi_kiran_hdmitx.c
index 328e584..49087ef 100644 (file)
--- a/drivers/gpu/drm/imx/hdp/API_AFE_ss28fdsoi_kiran_hdmitx.c
+++ b/drivers/gpu/drm/imx/hdp/API_AFE_ss28fdsoi_kiran_hdmitx.c
@@ -578,93 +578,6 @@ int phy_cfg_hdp_ss28fdsoi(state_struct *state, int num_lanes,
 
 }
 
-static void arc_power_up(state_struct *state)
-{
-       DRM_DEBUG("arc_power_up()\n");
-
-       /* register CMN_RXCAL_OVRD */
-       Afe_write(state, 0x5025, 0x0001);
-}
-
-static void arc_calibrate(state_struct *state)
-{
-       uint16_t txpu_calib_code;
-       uint16_t txpd_calib_code;
-       uint16_t txpu_adj_calib_code;
-       uint16_t txpd_adj_calib_code;
-       uint16_t prev_calib_code;
-       uint16_t new_calib_code;
-       uint16_t rdata;
-
-       DRM_DEBUG("aux_cal_cfg() ARC programming\n");
-       /* register TX_DIG_CTRL_REG_2 */
-       prev_calib_code = Afe_read(state, 0x5024);
-       /* register CMN_TXPUCAL_CTRL */
-       txpu_calib_code = Afe_read(state, 0x00E0);
-       /* register CMN_TXPDCAL_CTRL */
-       txpd_calib_code = Afe_read(state, 0x00F0);
-       /* register CMN_TXPU_ADJ_CTRL */
-       txpu_adj_calib_code = Afe_read(state, 0x0108);
-       /* register CMN_TXPD_ADJ_CTRL */
-       txpd_adj_calib_code = Afe_read(state, 0x010c);
-
-       new_calib_code = ((txpu_calib_code + txpd_calib_code) / 2)
-           + txpu_adj_calib_code + txpd_adj_calib_code;
-
-       if (new_calib_code != prev_calib_code) {
-               /* register TX_ANA_CTRL_REG_1 */
-               rdata = Afe_read(state, 0x5020);
-               rdata &= 0xDFFF;
-               /* register TX_ANA_CTRL_REG_1 */
-               Afe_write(state, 0x5020, rdata);
-               /* register TX_DIG_CTRL_REG_2 */
-               Afe_write(state, 0x5024, new_calib_code);
-               mdelay(10);
-               rdata |= 0x2000;
-               /* register TX_ANA_CTRL_REG_1 */
-               Afe_write(state, 0x5020, rdata);
-               udelay(150);
-       }
-}
-
-static void arc_config(state_struct *state)
-{
-       DRM_DEBUG("arc_config() ARC programming\n");
-
-       /* register TX_ANA_CTRL_REG_2 */
-       Afe_write(state, 0x5021, 0x0100);
-       udelay(100);
-       /* register TX_ANA_CTRL_REG_2 */
-       Afe_write(state, 0x5021, 0x0300);
-       udelay(100);
-       /* register TX_ANA_CTRL_REG_3 */
-       Afe_write(state, 0x5026, 0x0000);
-       udelay(100);
-       /* register TX_ANA_CTRL_REG_1 */
-       Afe_write(state, 0x5020, 0x2008);
-       udelay(100);
-       /* register TX_ANA_CTRL_REG_1 */
-       Afe_write(state, 0x5020, 0x2018);
-       udelay(100);
-       /* register TX_ANA_CTRL_REG_1 */
-       Afe_write(state, 0x5020, 0x2098);
-       /* register TX_ANA_CTRL_REG_2 */
-       Afe_write(state, 0x5021, 0x030C);
-       /* register TX_ANA_CTRL_REG_5 */
-       Afe_write(state, 0x5029, 0x0000);
-       udelay(100);
-       /* register TX_ANA_CTRL_REG_4 */
-       Afe_write(state, 0x5027, 0x4001);
-       mdelay(5);
-       /* register TX_ANA_CTRL_REG_1 */
-       Afe_write(state, 0x5020, 0x2198);
-       mdelay(5);
-       /* register TX_ANA_CTRL_REG_2 */
-       Afe_write(state, 0x5021, 0x030D);
-       udelay(100);
-       Afe_write(state, 0x5021, 0x030F);
-}
-
 int hdmi_tx_kiran_power_configuration_seq(state_struct *state, int num_lanes)
 {
        /* Configure the power state. */

diff --git a/drivers/gpu/drm/imx/hdp/API_AFE_t28hpc_hdmitx.c b/drivers/gpu/drm/imx/hdp/API_AFE_t28hpc_hdmitx.c
index 74cfaf4..bc2ce2a 100644 (file)
--- a/drivers/gpu/drm/imx/hdp/API_AFE_t28hpc_hdmitx.c
+++ b/drivers/gpu/drm/imx/hdp/API_AFE_t28hpc_hdmitx.c
@@ -1825,93 +1825,6 @@ int phy_cfg_t28hpc(state_struct *state, int num_lanes, VIC_MODES vicMode, int bp
 
 }
 
-static void arc_power_up(state_struct *state)
-{
-       DRM_DEBUG("arc_power_up()\n");
-
-       /* register CMN_RXCAL_OVRD */
-       Afe_write(state, 0x5025, 0x0001);
-}
-
-static void arc_calibrate(state_struct *state)
-{
-       uint16_t txpu_calib_code;
-       uint16_t txpd_calib_code;
-       uint16_t txpu_adj_calib_code;
-       uint16_t txpd_adj_calib_code;
-       uint16_t prev_calib_code;
-       uint16_t new_calib_code;
-       uint16_t rdata;
-
-       DRM_DEBUG("aux_cal_cfg() ARC programming\n");
-       /* register TX_DIG_CTRL_REG_2 */
-       prev_calib_code = Afe_read(state, 0x5024);
-       /* register CMN_TXPUCAL_CTRL */
-       txpu_calib_code = Afe_read(state, 0x00E0);
-       /* register CMN_TXPDCAL_CTRL */
-       txpd_calib_code = Afe_read(state, 0x00F0);
-       /* register CMN_TXPU_ADJ_CTRL */
-       txpu_adj_calib_code = Afe_read(state, 0x0108);
-       /* register CMN_TXPD_ADJ_CTRL */
-       txpd_adj_calib_code = Afe_read(state, 0x010c);
-
-       new_calib_code = ((txpu_calib_code + txpd_calib_code) / 2)
-               + txpu_adj_calib_code + txpd_adj_calib_code;
-
-       if (new_calib_code != prev_calib_code) {
-               /* register TX_ANA_CTRL_REG_1 */
-               rdata = Afe_read(state, 0x5020);
-               rdata &= 0xDFFF;
-               /* register TX_ANA_CTRL_REG_1 */
-               Afe_write(state, 0x5020, rdata);
-               /* register TX_DIG_CTRL_REG_2 */
-               Afe_write(state, 0x5024, new_calib_code);
-               mdelay(10);
-               rdata |= 0x2000;
-               /* register TX_ANA_CTRL_REG_1 */
-               Afe_write(state, 0x5020, rdata);
-               udelay(150);
-       }
-}
-
-static void arc_config(state_struct *state)
-{
-       DRM_DEBUG("arc_config() ARC programming\n");
-
-       /* register TX_ANA_CTRL_REG_2 */
-       Afe_write(state, 0x5021, 0x0100);
-       udelay(100);
-       /* register TX_ANA_CTRL_REG_2 */
-       Afe_write(state, 0x5021, 0x0300);
-       udelay(100);
-       /* register TX_ANA_CTRL_REG_3 */
-       Afe_write(state, 0x5026, 0x0000);
-       udelay(100);
-       /* register TX_ANA_CTRL_REG_1 */
-       Afe_write(state, 0x5020, 0x2008);
-       udelay(100);
-       /* register TX_ANA_CTRL_REG_1 */
-       Afe_write(state, 0x5020, 0x2018);
-       udelay(100);
-       /* register TX_ANA_CTRL_REG_1 */
-       Afe_write(state, 0x5020, 0x2098);
-       /* register TX_ANA_CTRL_REG_2 */
-       Afe_write(state, 0x5021, 0x030C);
-       /* register TX_ANA_CTRL_REG_5 */
-       Afe_write(state, 0x5029, 0x0000);
-       udelay(100);
-       /* register TX_ANA_CTRL_REG_4 */
-       Afe_write(state, 0x5027, 0x4001);
-       mdelay(5);
-       /* register TX_ANA_CTRL_REG_1 */
-       Afe_write(state, 0x5020, 0x2198);
-       mdelay(5);
-       /* register TX_ANA_CTRL_REG_2 */
-       Afe_write(state, 0x5021, 0x030D);
-       udelay(100);
-       Afe_write(state, 0x5021, 0x030F);
-}
-
 int hdmi_tx_t28hpc_power_config_seq(state_struct *state, int num_lanes)
 {
        unsigned char k;

diff --git a/drivers/gpu/drm/imx/hdp/Makefile b/drivers/gpu/drm/imx/hdp/Makefile
index 4750aee..20bdab8 100644 (file)
--- a/drivers/gpu/drm/imx/hdp/Makefile
+++ b/drivers/gpu/drm/imx/hdp/Makefile
@@ -1,5 +1,5 @@
 obj-$(CONFIG_DRM_IMX_HDP) += imx-hdp.o \
-                       imx-dp.o imx-hdmi.o \
+                       imx-dp.o imx-hdmi.o imx-arc.o\
                        API_AFE_ss28fdsoi_kiran_hdmitx.o \
                        API_AFE_t28hpc_hdmitx.o \
                        ss28fdsoi_hdmitx_table.o \

diff --git a/drivers/gpu/drm/imx/hdp/imx-arc.c b/drivers/gpu/drm/imx/hdp/imx-arc.c
new file mode 100644 (file)
index 0000000..b6774c5
--- /dev/null
+++ b/drivers/gpu/drm/imx/hdp/imx-arc.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "imx-hdp.h"
+
+void imx_arc_power_up(state_struct *state)
+{
+       DRM_DEBUG("arc_power_up()\n");
+
+       /* register CMN_RXCAL_OVRD */
+       Afe_write(state, 0x5025, 0x0001);
+}
+
+void imx_arc_calibrate(state_struct *state)
+{
+       u16 txpu_calib_code;
+       u16 txpd_calib_code;
+       u16 txpu_adj_calib_code;
+       u16 txpd_adj_calib_code;
+       u16 prev_calib_code;
+       u16 new_calib_code;
+       u16 rdata;
+
+       DRM_DEBUG("aux_cal_cfg() ARC programming\n");
+       /* register TX_DIG_CTRL_REG_2 */
+       prev_calib_code = Afe_read(state, 0x5024);
+       /* register CMN_TXPUCAL_CTRL */
+       txpu_calib_code = Afe_read(state, 0x00E0);
+       /* register CMN_TXPDCAL_CTRL */
+       txpd_calib_code = Afe_read(state, 0x00F0);
+       /* register CMN_TXPU_ADJ_CTRL */
+       txpu_adj_calib_code = Afe_read(state, 0x0108);
+       /* register CMN_TXPD_ADJ_CTRL */
+       txpd_adj_calib_code = Afe_read(state, 0x010c);
+
+       new_calib_code = ((txpu_calib_code + txpd_calib_code) / 2)
+               + txpu_adj_calib_code + txpd_adj_calib_code;
+
+       if (new_calib_code != prev_calib_code) {
+               /* register TX_ANA_CTRL_REG_1 */
+               rdata = Afe_read(state, 0x5020);
+               rdata &= 0xDFFF;
+               /* register TX_ANA_CTRL_REG_1 */
+               Afe_write(state, 0x5020, rdata);
+               /* register TX_DIG_CTRL_REG_2 */
+               Afe_write(state, 0x5024, new_calib_code);
+               mdelay(10);
+               rdata |= 0x2000;
+               /* register TX_ANA_CTRL_REG_1 */
+               Afe_write(state, 0x5020, rdata);
+               udelay(150);
+       }
+}
+
+void imx_arc_config(state_struct *state)
+{
+       DRM_DEBUG("arc_config() ARC programming\n");
+
+       /* register TX_ANA_CTRL_REG_2 */
+       Afe_write(state, 0x5021, 0x0100);
+       udelay(100);
+       /* register TX_ANA_CTRL_REG_2 */
+       Afe_write(state, 0x5021, 0x0300);
+       udelay(100);
+       /* register TX_ANA_CTRL_REG_3 */
+       Afe_write(state, 0x5026, 0x0000);
+       udelay(100);
+       /* register TX_ANA_CTRL_REG_1 */
+       Afe_write(state, 0x5020, 0x2008);
+       udelay(100);
+       /* register TX_ANA_CTRL_REG_1 */
+       Afe_write(state, 0x5020, 0x2018);
+       udelay(100);
+       /* register TX_ANA_CTRL_REG_1 */
+       Afe_write(state, 0x5020, 0x2098);
+       /* register TX_ANA_CTRL_REG_2 */
+       Afe_write(state, 0x5021, 0x030C);
+       /* register TX_ANA_CTRL_REG_5 */
+       Afe_write(state, 0x5029, 0x0000);
+       udelay(100);
+       /* register TX_ANA_CTRL_REG_4 */
+       Afe_write(state, 0x5027, 0x4001);
+       mdelay(5);
+       /* register TX_ANA_CTRL_REG_1 */
+       Afe_write(state, 0x5020, 0x2198);
+       mdelay(5);
+       /* register TX_ANA_CTRL_REG_2 */
+       Afe_write(state, 0x5021, 0x030D);
+       udelay(100);
+       Afe_write(state, 0x5021, 0x030F);
+}
+

diff --git a/drivers/gpu/drm/imx/hdp/imx-hdp.h b/drivers/gpu/drm/imx/hdp/imx-hdp.h
index d656e7c..d2bb902 100644 (file)
--- a/drivers/gpu/drm/imx/hdp/imx-hdp.h
+++ b/drivers/gpu/drm/imx/hdp/imx-hdp.h
@@ -226,5 +226,8 @@ struct imx_hdp {
 };
 
 u32 imx_hdp_audio(AUDIO_TYPE type, u32 sample_rate, u32 channels, u32 width);
+void imx_arc_power_up(state_struct *state);
+void imx_arc_calibrate(state_struct *state);
+void imx_arc_config(state_struct *state);
 
 #endif