/*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
return;
}
+int cdns3_enable_clks(int index)
+{
+ init_clk_usb3(index);
+ return 0;
+}
+
+int cdns3_disable_clks(int index)
+{
+ sc_err_t err;
+ sc_ipc_t ipc;
+
+ ipc = gd->arch.ipc_channel_handle;
+
+ err = sc_pm_clock_enable(ipc, SC_R_USB_2, SC_PM_CLK_MISC, false, false);
+ if (err != SC_ERR_NONE)
+ printf("USB3 disable clock failed!, line=%d (error = %d)\n",
+ __LINE__, err);
+
+ err = sc_pm_clock_enable(ipc, SC_R_USB_2, SC_PM_CLK_MST_BUS, false, false);
+ if (err != SC_ERR_NONE)
+ printf("USB3 disable clock failed!, line=%d (error = %d)\n",
+ __LINE__, err);
+
+ err = sc_pm_clock_enable(ipc, SC_R_USB_2, SC_PM_CLK_PER, false, false);
+ if (err != SC_ERR_NONE)
+ printf("USB3 disable clock failed!, line=%d (error = %d)\n",
+ __LINE__, err);
+
+ return 0;
+}
void init_clk_usdhc(u32 index)
{