MLK-14897-1: clk: imx7d: do not set parent of ethernet ref clocks

This is a rebase ot upstream commit:
'commit 5e33ebff7edd ("clk: imx7d: do not set parent of ethernet
time/ref clocks")':

    "clk: imx7d: do not set parent of ethernet time/ref clocks

    All device trees currently in mainline specify the time clock parent
    using the assigned-clocks/assigned-clock-parents method, there is no
    need to statically assign the parent in the core clock driver.
    Also all current boards provide an Ethernet reference clock for the
    PHY externally, hence configuring the internal PHY reference clock.

    Furthermore, and the actual driver of this patch, specify ethernet
    related parents at that early point in boot leads to a warning:
    bad: scheduling from the idle thread!

    The reason for the warning is that setting the parent enables the ENET
    PLL since we are using CLK_OPS_PARENT_ENABLE. Enabling the ENET PLL can
    cause clk_pllv3_wait_lock to sleep. See also:
    commit fc8726a2c021 ("clk: core: support clocks which requires parents
    enable (part 2)").

    Note that setting the ENET AXI root clock parent also requires ENET
    PLL to be enabled. However, U-Boot typically leaves the ENET PLL on,
    hence when the framework sets the parent of the first clock, it does
    not need to wait for the PLL to come up. But because there is currently
    no user of that clock, the PLL gets disabled after setting the parent.
    Therefore, subsequent reparenting calls of any clock which somehow rely
    on the ENET PLL, need to reenable the ENET PLL which leads to a sleep.
    Removing those subsequent reparenting calls works around this issue.

    Also remove comments. The code is really verbose enough."

Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>

diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index ea82f46..8e6cc29 100644 (file)
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -905,15 +905,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
        /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
        imx_clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
 
-       /*
-        * init enet clock source:
-        *      AXI clock source is 250Mhz
-        *      Phy refrence clock is 25Mhz
-        *      1588 time clock source is 100Mhz
-        */
        imx_clk_set_parent(clks[IMX7D_ENET_AXI_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_250M_CLK]);
        imx_clk_set_rate(clks[IMX7D_ENET_AXI_ROOT_CLK], 267000000);
-       imx_clk_set_parent(clks[IMX7D_ENET_PHY_REF_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_25M_CLK]);
 
        /* set pcie root's parent clk source */
        imx_clk_set_parent(clks[IMX7D_PCIE_CTRL_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_250M_CLK]);