MLK-17586-3 i.MX7ULP: change USDHC clock rate

Change USDHC0 and USDHC1 per clock source from APLL_PFD1,
and set the APll_PFD1 clock rate to 352.8MHz.

Also gate off APll_PFD1/2/3 before boot OS, otherwise set
the clock rate of APll_PFD1/2/3 during OS boot up will triger
some warning message.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
(cherry picked from commit 07ef0fab23204684d82f27baf721a72b247f30c5)
(cherry picked from commit 1c30a73542990afbe48bf7a398baba9c5efaf4fe)
(cherry picked from commit 0e4ce4b6b3f8d06f5b63850e04a1e4deb9b07624)
(cherry picked from commit 113a509e4d4ea84b55b296efa5f760b7192f9487)
(cherry picked from commit e01af8fc7daf0700c13f46e985e2e956f753feff)

diff --git a/arch/arm/include/asm/arch-mx7ulp/scg.h b/arch/arm/include/asm/arch-mx7ulp/scg.h
index 3b5b7f6..59cb924 100644 (file)
--- a/arch/arm/include/asm/arch-mx7ulp/scg.h
+++ b/arch/arm/include/asm/arch-mx7ulp/scg.h
@@ -323,6 +323,7 @@ typedef struct scg_regs {
 
 u32 scg_clk_get_rate(enum scg_clk clk);
 int scg_enable_pll_pfd(enum scg_clk clk, u32 frac);
+int scg_disable_pll_pfd(enum scg_clk clk);
 int scg_enable_usb_pll(bool usb_control);
 u32 decode_pll(enum pll_clocks pll);
 

diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c
index 6191153..65201d1 100644 (file)
--- a/arch/arm/mach-imx/mx7ulp/clock.c
+++ b/arch/arm/mach-imx/mx7ulp/clock.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
  */
 
 #include <common.h>
@@ -151,8 +152,8 @@ void init_clk_usdhc(u32 index)
                /*Disable the clock before configure it */
                pcc_clock_enable(PER_CLK_USDHC0, false);
 
-               /* 158MHz / 1 = 158MHz */
-               pcc_clock_sel(PER_CLK_USDHC0, SCG_NIC1_CLK);
+               /* 352.8MHz / 1 = 352.8MHz */
+               pcc_clock_sel(PER_CLK_USDHC0, SCG_APLL_PFD1_CLK);
                pcc_clock_div_config(PER_CLK_USDHC0, false, 1);
                pcc_clock_enable(PER_CLK_USDHC0, true);
                break;
@@ -160,9 +161,9 @@ void init_clk_usdhc(u32 index)
                /*Disable the clock before configure it */
                pcc_clock_enable(PER_CLK_USDHC1, false);
 
-               /* 158MHz / 1 = 158MHz */
-               pcc_clock_sel(PER_CLK_USDHC1, SCG_NIC1_CLK);
-               pcc_clock_div_config(PER_CLK_USDHC1, false, 1);
+               /* 352.8MHz / 2 = 176.4MHz */
+               pcc_clock_sel(PER_CLK_USDHC1, SCG_APLL_PFD1_CLK);
+               pcc_clock_div_config(PER_CLK_USDHC1, false, 2);
                pcc_clock_enable(PER_CLK_USDHC1, true);
                break;
        default:
@@ -305,8 +306,8 @@ void clock_init(void)
 
        scg_a7_init_core_clk();
 
-       /* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */
-       scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35);
+       /* APLL PFD1 = 352.8Mhz, PFD2=340.2Mhz, PFD3=793.8Mhz */
+       scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 27);
        scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28);
        scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12);
 

diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c
index 4c06655..275311d 100644 (file)
--- a/arch/arm/mach-imx/mx7ulp/scg.c
+++ b/arch/arm/mach-imx/mx7ulp/scg.c
@@ -715,6 +715,61 @@ int scg_enable_pll_pfd(enum scg_clk clk, u32 frac)
        return 0;
 }
 
+int scg_disable_pll_pfd(enum scg_clk clk)
+{
+       u32 reg;
+       u32 gate;
+       u32 addr;
+
+       switch (clk) {
+       case SCG_SPLL_PFD0_CLK:
+       case SCG_APLL_PFD0_CLK:
+               gate = SCG_PLL_PFD0_GATE_MASK;
+
+               if (clk == SCG_SPLL_PFD0_CLK)
+                       addr = (u32)(&scg1_regs->spllpfd);
+               else
+                       addr = (u32)(&scg1_regs->apllpfd);
+               break;
+       case SCG_SPLL_PFD1_CLK:
+       case SCG_APLL_PFD1_CLK:
+               gate = SCG_PLL_PFD1_GATE_MASK;
+
+               if (clk == SCG_SPLL_PFD1_CLK)
+                       addr = (u32)(&scg1_regs->spllpfd);
+               else
+                       addr = (u32)(&scg1_regs->apllpfd);
+               break;
+       case SCG_SPLL_PFD2_CLK:
+       case SCG_APLL_PFD2_CLK:
+               gate = SCG_PLL_PFD2_GATE_MASK;
+
+               if (clk == SCG_SPLL_PFD2_CLK)
+                       addr = (u32)(&scg1_regs->spllpfd);
+               else
+                       addr = (u32)(&scg1_regs->apllpfd);
+               break;
+       case SCG_SPLL_PFD3_CLK:
+       case SCG_APLL_PFD3_CLK:
+               gate = SCG_PLL_PFD3_GATE_MASK;
+
+               if (clk == SCG_SPLL_PFD3_CLK)
+                       addr = (u32)(&scg1_regs->spllpfd);
+               else
+                       addr = (u32)(&scg1_regs->apllpfd);
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       /* Gate the PFD */
+       reg = readl(addr);
+       reg |= gate;
+       writel(reg, addr);
+
+       return 0;
+}
+
 #define SIM_MISC_CTRL0_USB_PLL_EN_MASK (0x1 << 2)
 int scg_enable_usb_pll(bool usb_control)
 {

diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index 9e21457..dd31965 100644 (file)
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
  */
 
 #include <common.h>
@@ -367,6 +368,13 @@ static char *get_reset_cause(char *ret)
        return ret;
 }
 
+void arch_preboot_os(void)
+{
+       scg_disable_pll_pfd(SCG_APLL_PFD1_CLK);
+       scg_disable_pll_pfd(SCG_APLL_PFD2_CLK);
+       scg_disable_pll_pfd(SCG_APLL_PFD3_CLK);
+}
+
 #ifdef CONFIG_ENV_IS_IN_MMC
 __weak int board_mmc_get_env_dev(int devno)
 {