<&clks IMX6UL_CLK_SAI2>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <0>, <12288000>;
-
+ somdevices,sai-mclk-direction-output;
status = "disabled";
};
}
+void __init imx6ul_sai_clk_init(void)
+{
+ struct device_node *np;
+ np = of_find_node_with_property(NULL, "somdevices,sai-mclk-direction-output");
+ if (np) {
+ //If exist the property
+ if (of_device_is_available(np)) {
+ //If the node is available
+ struct regmap *gpr;
+ volatile uint32_t* pad_mck;
+ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
+ if (!IS_ERR(gpr)) {
+ //Set SAI2_MCLK as output
+ regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_SAI2_MCLK_DIR,
+ MCLK_DIR(2));
+ //Set MUX SAI2_MCLK to JTAG_TMS pin
+ pad_mck = (volatile uint32_t*)ioremap(0x020e0048, 16);
+ writel(0x2, pad_mck);
+ }
+ else
+ pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");
+ }
+ }
+}
+
static int ksz8081_phy_fixup(struct phy_device *dev)
{
if (dev && dev->interface == PHY_INTERFACE_MODE_MII) {
imx6ul_enet_init();
imx_anatop_init();
imx6ul_pm_init();
+ imx6ul_sai_clk_init();
}
static void __init imx6ul_init_irq(void)